Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage

LIU Wei; WEI Zhigang; DU Wei; CAO Guangyi; WANG Wei

doi:10.11999/JEIT170989

Volume 40 Issue 7

Jul. 2018

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Article Navigation > Journal of Electronics & Information Technology > 2018 > 40(7): 1759-1766

LIU Wei, WEI Zhigang, DU Wei, CAO Guangyi, WANG Wei. Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage[J]. Journal of Electronics & Information Technology, 2018, 40(7): 1759-1766. doi: 10.11999/JEIT170989

Citation:

LIU Wei, WEI Zhigang, DU Wei, CAO Guangyi, WANG Wei. Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage[J]. Journal of Electronics & Information Technology, 2018, 40(7): 1759-1766. doi: 10.11999/JEIT170989

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Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage

doi: 10.11999/JEIT170989

LIU Wei^①② WEI Zhigang^① DU Wei^①② CAO Guangyi^① WANG Wei^③

Funds:

The National Natural Science Foundation of China (61672384), The Ministry of Education of Humanities and Social Science project (16YJCZH014), The Natural Science Foundation of Hubei Province (2016CFB466), The Fundamental Research Funds for the Central Universities (WUT: 2016III028, 2017III028-005), Major Program of Technical Innovation Special Program in Hubei Province of China (2017AAA122)

Received Date: 2017-10-23
Rev Recd Date: 2018-04-03
Publish Date: 2018-07-19

Abstract

Abstract

Near-threshold voltage computing enables transistor voltage scaling to continue with Moore’s Law projection and dramatically improves power and energy efficiency. However, a great number of bit-cell errors occur in large SRAM structures, such as Last-Level Cache (LLC). A Fault-Tolerant LLC (FTLLC) design with conventional 6T SRAM cells is proposed to deal with a higher failure rate which is more than 1% at near-threshold voltage. FTLLC improves the reliability of data stored in Cache by correcting the single-error and compressing multi-errors in Cache entry. To validate the efficiency of FTLLC, FTLLC and prior works are implemented in gem5, and are simulated with SPEC CPU2006. The experiment shows that compared with Concertina at 650 mV, the performance of a 65 nm FTLLC with 4-Byte subblock size improves by 7.2% and the Cache capacity increases by 24.9%. Besides, the miss rate decreases by 58.2%, and there are little increases on area overhead and power consumption.
- Near-threshold voltage、Fault-tolerant Cache、Error correction code、Compression mechanism,

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References(20)

References

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