Design of Hardware Obfuscation AES Based on State Deflection Strategy

doi:10.11999/JEIT170556

Volume 40 Issue 3

Mar. 2018

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Article Navigation > Journal of Electronics & Information Technology > 2018 > 40(3): 750-757

Design of Hardware Obfuscation AES Based on State Deflection Strategy[J]. Journal of Electronics & Information Technology, 2018, 40(3): 750-757. doi: 10.11999/JEIT170556

Citation:

Design of Hardware Obfuscation AES Based on State Deflection Strategy[J]. Journal of Electronics & Information Technology, 2018, 40(3): 750-757. doi: 10.11999/JEIT170556

Design of Hardware Obfuscation AES Based on State Deflection Strategy[J]. Journal of Electronics & Information Technology, 2018, 40(3): 750-757. doi: 10.11999/JEIT170556

Citation:

Design of Hardware Obfuscation AES Based on State Deflection Strategy[J]. Journal of Electronics & Information Technology, 2018, 40(3): 750-757. doi: 10.11999/JEIT170556

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Design of Hardware Obfuscation AES Based on State Deflection Strategy

doi: 10.11999/JEIT170556 cstr: 32379.14.JEIT170556

Funds:

The Zhejiang Provincial Natural Science Foundation (LY18F040002), The National Natural Science Foundation of China (61404076, 61474068), The ST Plan of Zhejiang Provincial Science and Technology Department (2015C 31010, 2016C31078), The Ningbo Natural Science Foundation (2014A610148, 2015A610107), The K. C. Wong Magna Fund in Ningbo University, China

Received Date: 2017-06-09
Rev Recd Date: 2017-11-15
Publish Date: 2018-03-19

Abstract

Abstract

Obfuscation is used to safeguard lawful rights and interests of developers and users in software security, by protecting critical information and algorithms with the system logic relation. Also, how to achieve obfuscation method to protect the hardware IP core is becoming an urgent problem. In this paper, a hardware obfuscation scheme based on deflection strategy is proposed by studying the obfuscation method and the AES algorithm. The deflection strategy with redundancy and black hole states are used to realize the Finite State Machine (FSM) obfuscation, and the bit flip method is used to realize the combinational logic obfuscation. Finally, the proposed hardware obfuscation AES algorithm is designed in SMIC 65 nm CMOS process. The parameters of toggle, data correlation and code coverage are selected to evaluate the efficiency and effectiveness of hardware confusion. Experimental results show that the area and power consumption of the hardware obfuscation AES algorithm is increased by 9% and 16% respectively, and the code coverage rate is over 93%.
- State deflection,
- Hardware obfuscation,
- AES algorithm,
- Reverse engineering,
- IP security

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References(19)

References

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