Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor

ZHANG Jingbo; YANG Zhiping; PENG Chunyu; DING Penghui; WU Xiulong

doi:10.11999/JEIT170547

Volume 39 Issue 11

Nov. 2017

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(11): 2755-2762

ZHANG Jingbo, YANG Zhiping, PENG Chunyu, DING Penghui, WU Xiulong. Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor[J]. Journal of Electronics & Information Technology, 2017, 39(11): 2755-2762. doi: 10.11999/JEIT170547

Citation:

ZHANG Jingbo, YANG Zhiping, PENG Chunyu, DING Penghui, WU Xiulong. Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor[J]. Journal of Electronics & Information Technology, 2017, 39(11): 2755-2762. doi: 10.11999/JEIT170547

Citation:

PDF( 1271 KB)

Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor

doi: 10.11999/JEIT170547

1.
2.
(School of Electronics and Information Engineering, Anhui University, Hefei 230601, China)

Funds:

The National Natural Science Foundation of China (61674002, 61474001, 61574001)

Received Date: 2017-06-08
Rev Recd Date: 2017-08-31
Publish Date: 2017-11-19

Abstract

Abstract

Based on Synopsys TCAD 3-D device simulation, the effects of PMOS transistor process parameters on the upset and recovery effect of Static Random Access Memory (SRAM) memory cell are studied in a 65-nm bulk CMOS technology, mainly by changing the three process parameters. The simulation results show that reducing the doping concentration of deep-P+-well, N-well and threshold doping concentration in PMOS transistor can decrease the Linear Energy Transfer (LET) value of the upset and recovery. By reducing the doping concentration of deep-P+-well and N-well in PMOS transistor, the time of the upset and recovery increases. The conclusion of this paper is helpful to optimize the design of Static Random Access Memory cell mitigating Single-Event Effect (SEE), and can gives a great guidance for the anti-radiation integrated circuit under bulk CMOS process.
- Static Random Access Memory (SRAM),
- Linear Energy Transfer (LET) value,
- Time of the upset and recovery,
- Single-Event Effect (SEE)

FullText(HTML)

References(23)

References

DODD P E and MASSENGILL L W. Basic mechanisms and modeling of single-event upset in digital microelectronics[J]. IEEE Transactions on Nuclear Science, 2003, 50(3): 583-602. doi: 10.1109/TNS.2003.813129.

KANG M, KIM J, and CHANG I J. Studying the variation effects of radiation hardened Quatro SRAM bit-cell[J]. IEEE Transactions on Nuclear Science, 2016, 63(4): 2399-2401. doi: 10.1109/TNS.2016.2590426.

KERNS S E, SHAFER B D, ROCKETT L R, et al. The design of radiation-hardened ICs for space: A compendium of approaches[J]. Proceedings of the IEEE, 1988, 76(11): 1470-1509. doi: 10.1109/5.90115.

LIU M S, LIU H Y, BREWSTER N, et al. Limiting upset cross sections of SEU hardened SOI SRAMs[J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3487-3493. doi: 10.1109/TNS.2006.886216.

CALIN T, NICOLAIDIS M, and VELAZCO R. Upset hardened memory design for submicron CMOS technology[J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874-2878. doi: 10.1109/23.556880.

WANG H B, LI Y Q, CHEN L, et al. An SEU-tolerant DICE latch design with feedback transistors[J]. IEEE Transactions on Nuclear Science, 2015, 62(2): 548-554. doi: 10.1109/TNS. 2015.2399019.

刘凡宇, 刘衡竹, 刘必慰, 等. 90 nm CMOS工艺下p+深阱掺杂浓度对电荷共享的影响[J]. 物理学报, 2011, 60(4): 461-468.

LIU Fanyu, LIU Hengzhu, LIU Biwei, et al. Effect of doping concentration in p+ deep well on charge sharing in 90 nm CMOS technology[J]. Acta Physica Sinica, 2011, 60(4): 461-468.

SAXENA P K and BHAT N. Process technique for SEU reliability improvement of deep sub-micron SRAM cell[J]. Solid-State Electronics, 2003, 47(4): 661-664. doi: 10.1016/ S0038-1101(02)00329-5.

DASGUPTA S, WITULSKI A F, BHUVA B L, et al. Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS[J]. IEEE Transactions on Nuclear Science, 2007, 54(6): 2407-2412. doi: 10.1109/TNS. 2007.910863.

LI Peng, ZHANG Minxuan, ZHAO Zhenyu, et al. A novel single event upset reversal in 40-nm bulk CMOS 6 T SRAM cells[J]. Nuclear Science and Techniques, 2015, 26(5): 76-82. doi: 10.13538/j.1001-8042/nst.26.050405.

MASSENGILL L W, AMUSAN O A, DASGUPTA S, et al. Soft-error charge-sharing mechanisms at sub-100 nm technology nodes[C]. IEEE International Conference on Integrated Circuit Design and Technology, Austin, TX, USA, 2007: 1-4. doi: 10.1109/ICICDT.2007.4299576.

HE Yibai and CHEN Shuming. Simulation study of the selectively implanted deep-N-well for PMOS SET mitigation [J]. IEEE Transactions on Device Materials Reliability, 2014, 14(1): 99-103. doi: 10.1109/TDMR.2013.2290032.

BLACK J D, BALL II D R, ROBINSON W H, et al. Characterizing SRAM single event upset in terms of single and multiple node charge collection[J]. IEEE Transactions on Nuclear Science, 2008, 55(6): 2943-2947. doi: 10.1109/TNS. 2008.2007231.

AMUSAN O A, MASSENGILL L W, BHUVA B L, et al. Design techniques to reduce SET pulse widths in deep- submicron combinational logic[J]. IEEE Transactions on Nuclear Science, 2007, 54(6): 2060-2064. doi: 10.1109/TNS. 2007.907754.

HSIEH C M, MURLEY P C, and O,BRIEN R R. A field-funneling effect on the collection of alpha-particle- generated carriers in silicon devices[J]. IEEE Electron Device Letters, 1981, 2(4): 103-105. doi: 10.1109/EDL.1981.25357.

AMUSAN O A, WITULSKI A F, MASSENGILL L W, et al. Charge collection and charge sharing in a 130 nm CMOS technology[J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3253-3258. doi: 10.1109/TNS.2006.884788.

CHEN Meng, LEI Jiefeng, HUANG Shengxiang, et al. Poly-Si TFTs integrated gate driver circuit with charge- sharing structure[J]. Journal of Semiconductors, 2017, 38(5): 92-97. doi: 10.1088/1674-4926/38/5/055001.

HE Liang, CHEN Hua, SUN Peng, et al. Single event upset rate modeling for ultra-deep submicron complementary metal-oxide-semiconductor devices[J]. Science China Information Sciences, 2016, 59(4): 1-11. doi: 10.1007/s11432- 015-5362-2.

CHUMAKOV A I. Modified charge collection model by point node for SEE sensitivity estimation[C]. 2015 IEEE 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Moscow, Russia, 2015: 1-5. doi: 10.1109/RADECS.2015.7365635.

YAN S, ZHANG W, LI G, et al. 3-D simulation of charge collection in double-gate MOSFET under low-energy proton irradiation[C]. IEEE International Nanoelectronics Conference (INEC), Chengdu, China, 2016: 1-2. doi: 10.1109/ INEC.2016.7589258.

FURUTA J, YAMAMOTO R, KOBAYASHI K, et al. Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates[C]. IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA, 2012: SE. 5.1-SE.5.5. doi: 10.1109/IRPS.2012.6241930.

DING Yi, HU Jianguo, QIN Junrui, et al. Effect of body biasing on single-event induced charge collection in deep N-well technology[J]. Chinese Physics B, 2015, 24(7): 079401. doi: 10.1088/1674-1056/24/7/079401.

Relative Articles

Supplements(0)

Cited By

Proportional views