A Novel Low Power Consumption Soft Error-tolerant Latch

ZHANG Zhang; ZHOU Yucheng; LIU Juncheng; CHENG Xin; XIE Guangjun

doi:10.11999/JEIT170191

Volume 39 Issue 10

Oct. 2017

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Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(10): 2520-2525

ZHANG Zhang, ZHOU Yucheng, LIU Juncheng, CHENG Xin, XIE Guangjun. A Novel Low Power Consumption Soft Error-tolerant Latch[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191

Citation:

ZHANG Zhang, ZHOU Yucheng, LIU Juncheng, CHENG Xin, XIE Guangjun. A Novel Low Power Consumption Soft Error-tolerant Latch[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191

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A Novel Low Power Consumption Soft Error-tolerant Latch

doi: 10.11999/JEIT170191

Funds:

The National Natural Science Foundation of China (61404043, 61674049, 61401137)

Received Date: 2017-03-03
Rev Recd Date: 2017-07-07
Publish Date: 2017-10-19

Abstract

Abstract

A novel C-element connect method is proposed. The gate of P-type/N-type transistor is modified from the top/bottom of conventional C-element to connect to output, which takes advantage of the transistor,s own feedback mechanism to form a feedback path to achieve the self-recovery function. Therefore, the dynamic performance and hardware overhead are significant reduced. The node-enhanced C-element is used as the output stage circuit and optimized, making the circuit more resistant to single event upset. Based on the above description, a novel soft error-tolerant latch is proposed. Due to the only transmission gate in the shortest route between input and output, the delay in signal transmission is reduced. The critical charge can be further enhanced by using feedback comparison mechanism. Compared with latches in literature at 22 nm CMOS process, the results show that the proposed latch performs greater in reliability and the power delay products improvement of proposed latch achieves 26.74%~97.50%.
- Latch,
- Soft error,
- C-element,
- Self-recovery

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References(21)

References

KATERINA Katsarou and YIORGOS Tsiatouhas. Soft error immune latch under SEU related double-node charge collection[C]. Proceedings of IEEE 21st International On-Line Testing Symposium (IOLTS), Halkidiki, 2015: 46-49. doi: 10.1109/IOLTS.2015.7229830.

ZIVANOV N M and MARCUESCU D. A systematic approach to modeling and analysis of transient fault in logic circuits[C]. Proceedings of Quality of Electronic Design, California, USA, 2009: 408-413. doi: 10.1109/ISQED.2009. 4810329.

GANGADHAR S, SKOUFIS M, and TRAGOUDAS S. Propagation of transients along sensitizable path[C]. Proceedings of IEEE International On-Line Testing Symposium, Greece, 2008: 129-134. doi: 10.1109/IOLTS. 2008.46.

HIEOKI Ueno and KAZUTERU Namba. Construction of a soft error (SEU) hardened latch with high critical charge[C]. Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Storrs, 2016: 27-30. doi: 10.1109/DFT.2016.7684064.

WANG H B, LI Y Q, CHEN L, et al. An SEU-tolerant DICE latch design with feedback transistors[J]. IEEE Transactions on Nuclear Science, 2015, 62(2): 548-554. doi: 10.1109/TNS.2015.2399019.

MEIERAN E S, ENGAL P R, and MAY T C. Measurement of alpha particle radioactivity in IC device packages[C]. Proceedings of 17th International Reliability Physics Symposium, New York, 1979: 13-22. doi: 10.1109/IRPS.1979. 362865.

BAUMANN R C. Radiation-induced soft-errors in advanced semiconductor technologies[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 305-316. doi: 10.1109/ TDMR.2005.853449.

黄正峰, 陈凡, 蒋翠云, 等. 基于时序优先的电路容错混合加固方案[J]. 电子与信息学报, 2014, 36(1): 234-240. doi: 10.3724/SP.J.1146.2013.00449.

HUANG Zhengfeng, CHEN Fan, JIANG Cuiyun, et al. A hybrid hardening strategy for circuit soft-error-tolerance based on timing priority[J]. Journal of Electronics Information Technology, 2014, 36(1): 234-240. doi: 10.3724 /SP.J.1146.2013.00449.

MOHAMMAD Saeed Ansari, MAHANI Ali, and HAN Jie. A novel gate grading approach for soft error tolerance in combinational circuits[C]. Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, 2016: 1-4. doi: 10.1109/CCECE.2016. 7726658.

IBE E, TANIGUCHI H, YAHAGI Y, et al. Impact of scaling on Neutron-Induced soft error in SRAMs from a 250 nm to a 22 nm design rule[J]. IEEE Transactions on Electron Devices, 2010, 57(7): 1527-1538. doi: 10.1109/TED.2010.2047907.

MITRA S, IYTER R, RAVISHARKAR K, et al. Reliable system design: Models, metrics and design techniques[C]. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, California, USA, 2008. doi: 10.1109 /ICCAD.2008.4681534.

WEY Ichyn, YANG Yusheng, WU Bincheng, et al. A low power-delay-product and robust Isolated-DICE based SEU- tolerant latch circuit design[J]. Microelectronics Journal, 2014, 45(1): 1-13. doi: 10.1016/j.mejo.2013.09.007.

FAZELI M, MIREMADI S G, EJLALI A, et al. Low energy single event upset/single event Transient-Tolerant latch for deep submicron technologies[J]. IET Computer Digital Techniques, 2009, 3(3): 289-303. doi: 10.1049/iet-cdt.2008. 0099.

NAN H and CHOI K. Novel soft error hardening design of nanoscale CMOS latch[C]. Proceedings of International Soc Design Conference, South Korea, 2010: 111-114. doi: 10.1109 /SOCDC.2010.5682959.

NAN Haiqing and CHOI Ken. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(7): 1445-1457. doi: 10.1109/TCSI.2011.2177135.

OMANA M, ROSSI D, and METRA C. Latch susceptibility to transient faults and new hardening approach[J]. IEEE Transactions on Computers, 2007, 56(9): 1255-1268. doi: 10.1109/TC.2007.1070.

SASAKI Y, NAMBA K, and ITO H. Soft error masking circuit and latch using schmitt trigger circuit[C]. Proceedings of 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Virginia, 2006: 327-335. doi: 10.1109/DFT.2006.60.

ANJAN Kumar Pudi N S and MARYAM Shojaei Baghini. Robust soft error tolerant CMOS latch configurations[J]. IEEE Transactions on Computers, 2016, 65(9): 2820-2834. doi: 10.1109/TC.2015.2509983.

TAJIMA Saki and SHI Youhua. A low-power soft error tolerant latch scheme[C]. Proceedings of IEEE 11th International Conference on ASIC (ASICON), Chengdu, China, 2015: 1-4. doi: 10.1109/ASICON.2015.7516885.

HUANG Zhengfeng. A high performance SEU-Tolerant latch for nanoscale CMOS technology[C]. Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE), Dresden, 2014: 1-5. doi: 10.7873/DATE.2014.175.

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