Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop

TIAN Yuze; WANG Yu; DAI Haishan; FANG Hua; LIU Wenqing

doi:10.11999/JEIT170088

Volume 39 Issue 10

Oct. 2017

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Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(10): 2397-2403

TIAN Yuze, WANG Yu, DAI Haishan, FANG Hua, LIU Wenqing. Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2397-2403. doi: 10.11999/JEIT170088

Citation:

TIAN Yuze, WANG Yu, DAI Haishan, FANG Hua, LIU Wenqing. Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2397-2403. doi: 10.11999/JEIT170088

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Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop

doi: 10.11999/JEIT170088

Funds:

The National Natural Science Foundation of China (41275037), Anhui Province Outstanding Youth Science Foundation (1308085JGD03)

Received Date: 2017-01-23
Rev Recd Date: 2017-05-03
Publish Date: 2017-10-19

Abstract

Abstract

Under the condition of working in sun-synchronous orbit, the error correction strategy is put forward due to the error caused by the communication error. According to the complementary error characteristics between satellite clock and local clock, a Digital Phase Locked Loop (DPLL) is designed, which is applied to the low frequency input signal and the large frequency multiplication factor. The local clock tracks the satellite clock pulse phase fluctuations and eliminates the accumulate error constantly. The complete design is developed with Field Programmable Gate Array (FPGA) devices and the detailed theoretical analysis and experimental results are presented. Experiments show that the design of the clock source can correct the abnormal flip or lose of second pulse and jump or lose of broadcast time package constantly. It can enter the lock state in 5 input clock cycles, and the cumulative error is less than 100 s. It can be used as the local clock source of satellite borne equipment.
- Digital Phase Locked Loop (DPLL),
- Feedback control,
- Proportional integral control,
- Frequency- multiplier,
- FPGA

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References(28)

References

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