Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor

DAI Zibin; YI Suwen; LI Wei; NAN Longmei

doi:10.11999/JEIT161380

Volume 39 Issue 10

Oct. 2017

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DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380

Citation:

DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380

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Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor

doi: 10.11999/JEIT161380

1.
(PLA Information Engineering University, Zhengzhou 450000, China)
2.

Funds:

The National Natural Science Foundation of China (61404175)

Received Date: 2016-12-21
Rev Recd Date: 2017-03-06
Publish Date: 2017-10-19

Abstract

Abstract

To overcome the common problem of low flexibility and much resource in Elliptic Curve Cryptographic (ECC) processor, a quantitative evaluation on Area-Time product (AT) for parallel processing architecture of ECC processor is proposed by statistics and modeling, and a conclusion that 3-way processing architecture is optimal can be drawn. Besides, a separated and hierarchical storage structure is exploited to strengthen the efficiency of data interaction. At the same time, a modular arithmetic unit is designed with a high level of resource reuse. Using 90 nm CMOS technology, the proposed processor occupied1.62mm2 can perform the scalar multiplication in2.26 ms/612.4J overGF(2571) and 2.63 ms/665.4 J overGF(p521), respectively. Compared to other works, this processor is advantageous not only in flexibility and scalability but also in making a good compromise between the hardware and the speed.
- Elliptic Curve Cryptography (ECC),
- Parallel processing architecture,
- Quantitative evaluation,
- Separated and hierarchical storage structure,
- Resource reuse

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References(20)

References

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