An Efficient Mixed-mode Test-Per-Clock Scheme

LIU Tieqiao; NIU Xiaoyan; YANG Jie; MAO Feng

doi:10.11999/JEIT161202

Volume 39 Issue 9

Sep. 2017

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Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(9): 2266-2271

LIU Tieqiao, NIU Xiaoyan, YANG Jie, MAO Feng. An Efficient Mixed-mode Test-Per-Clock Scheme[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2266-2271. doi: 10.11999/JEIT161202

Citation:

LIU Tieqiao, NIU Xiaoyan, YANG Jie, MAO Feng. An Efficient Mixed-mode Test-Per-Clock Scheme[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2266-2271. doi: 10.11999/JEIT161202

LIU Tieqiao, NIU Xiaoyan, YANG Jie, MAO Feng. An Efficient Mixed-mode Test-Per-Clock Scheme[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2266-2271. doi: 10.11999/JEIT161202

Citation:

LIU Tieqiao, NIU Xiaoyan, YANG Jie, MAO Feng. An Efficient Mixed-mode Test-Per-Clock Scheme[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2266-2271. doi: 10.11999/JEIT161202

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An Efficient Mixed-mode Test-Per-Clock Scheme

doi: 10.11999/JEIT161202

Funds:

Zhejiang Provincial Natural Science Foundation (LQ15F040005)

Received Date: 2016-11-08
Rev Recd Date: 2017-04-10
Publish Date: 2017-09-19

Abstract

Abstract

A mixed-mode Test-Per-Clock Built In Self Test (BIST) scheme is proposed. The test consists of two parts: the free Linear Feedback Shift Register (LFSR) pseudo-random test mode and the deterministic test pattern based on controlled LFSR. Pseudo random test mode is used to quickly detect pseudo-random susceptible faults and reduce the deterministic data storage. Controlled LFSR test mode uses the control bits directly stored in the ROM to generate a deterministic test of the remaining faults. Based on the theoretical analysis of the proposed mixed-mode BIST test structure, a pseudo-random test sequence selection method and a deterministic test generation method based on controlled linear shifter are proposed. Simulation results on benchmark circuits show that the proposed method can obtain the complete single stuck-at fault coverage and has good stability in test generation. Compared with other methods, it has simpler Test Pattern Generator (TPG) design and lower test cost as well as shorter test application time.
- IC test,
- Built In Self Test (BIST),
- Test-Per-Clock test,
- Test generation

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References(21)

References

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