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Volume 39 Issue 7
Jul.  2017
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LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
Citation: LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096

Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model

doi: 10.11999/JEIT161096
Funds:

The National Natural Science Foundation of China (61371104)

  • Received Date: 2016-10-17
  • Rev Recd Date: 2017-01-24
  • Publish Date: 2017-07-19
  • Feedback structure is an efficient topology for noise-reducing in analog circuit while the cyclic circuit is widely used in digital circuit only for sequential circuit design due to its data-keeping property. However, few works study the reliability of the feedback structure for combinational circuits especially for the low power application. Many researchers pay their attentions to Markov Random Field (MRF) theory based circuits, which can operate in ultra-low supply voltage with high noise-immune. However, the MRF based circuit design methodology has a lack of the proof of the final feedback structures. Thus the reliability of MRF based feedback structures is not explained clearly. This paper uses the probabilistic CMOS model to analysis the NAND-NAND based feedback structure. The probability boundedness and increasing monotonicity properties of feedback structure are proved. Besides, it is proved that the feedback structure of MRF can achieve higher probability than the traditional design. In measurement, the result can support of proof and analysis.
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