Advanced Search
Volume 39 Issue 7
Jul.  2017
Turn off MathJax
Article Contents
LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
Citation: LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096

Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model

doi: 10.11999/JEIT161096
Funds:

The National Natural Science Foundation of China (61371104)

  • Received Date: 2016-10-17
  • Rev Recd Date: 2017-01-24
  • Publish Date: 2017-07-19
  • Feedback structure is an efficient topology for noise-reducing in analog circuit while the cyclic circuit is widely used in digital circuit only for sequential circuit design due to its data-keeping property. However, few works study the reliability of the feedback structure for combinational circuits especially for the low power application. Many researchers pay their attentions to Markov Random Field (MRF) theory based circuits, which can operate in ultra-low supply voltage with high noise-immune. However, the MRF based circuit design methodology has a lack of the proof of the final feedback structures. Thus the reliability of MRF based feedback structures is not explained clearly. This paper uses the probabilistic CMOS model to analysis the NAND-NAND based feedback structure. The probability boundedness and increasing monotonicity properties of feedback structure are proved. Besides, it is proved that the feedback structure of MRF can achieve higher probability than the traditional design. In measurement, the result can support of proof and analysis.
  • loading
  • SLOANE N J A, WYNER A D, and SHANNON C E. Collected Papers[M]. New York: Wiley-IEEE Press, 1993: 711-714. doi: 10.1109/9780470544242.ch50.
    RIVEST R L. The necessity of feedback in minimal monotone combinational circuits[J]. IEEE Transactions on Computers, 1997, C-26(6): 606-607. doi: 10.1109/TC.1977.1674886.
    STOK L. False loops through resource sharing[C]. IEEE/ ACM International Conference on Computer-aided Design, Santa Clara, CA, USA, 1992: 345-348. doi: 10.1109/ICCAD. 1992.279349.
    CHEN J H, CHEN Y C, and WENG W C. Synthesis and verification of cyclic combinational circuits[C]. IEEE International System-on-Chip Conference, Beijing, 2015: 257-262. doi: 10.1109/SOCC.2015.7406959.
    KUMER V. Design methodology for multiple output combinational circuits using cyclic combinational technique[J]. Journal of Circuits, Systems Computers, 2016, 25(12): 165013.
    RIEDEL M D and BURCK J. The synthesis of cyclic combinational circuits[C]. ACM Design Automation Conference. Anaheim, CA, 2003: 163-168. doi: 10.1145/ 775832.775875.
    BAHAR R and MUNDY J. A probabilistic-based design methodology for nanoscale computation[C]. IEEE/ACM International Conference on Computer-aided Design, San Jose, CA, USA, 2003: 480-486. doi: 10.1109/ICCAD.2003. 159727.
    NEPAL K, BAHAR R I, and MUNDY J. Designing logic circuits for probabilistic computation in the presence of noise[C]. ACM Design Automation Conference, Anaheim, CA, 2005: 485-490. doi: 10.1145/1065579.1065706.
    WEY I C, CHEN Y G, and YU C H. Design and implementation of cost-effective probabilistic-based noise- tolerant VLSI circuits[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2009, 56(11): 2411-2424. doi: 10.1109/TCSI.2009.2015648.
    LI Y, HU J, and LU H. Area-efficient partial-clique-energy MRF pair design with ultra-low supply voltage[C]. IEEE International Symposium on Circuits and Systems, Montreal, Canada, 2016: 261-264. doi: 10.1109/ISCAS.2016.7527220.
    LI Y, LI X, and HU J. Area-sharing cyclic structure MRF circuits design in ultra-low supply voltage[C]. IEEE International Symposium on Circuits and Systems, Lisbon, 2015: 2353-2356. doi: 10.1109/ISCAS.2015.7169156.
    WEY I C, CHEN Y G, and YU C. A 0.18 m probabilistic- based noise-tolerate circuit design and implementation with 28.7 dB noise-immunity improvement[C]. IEEE Asian Solid- State Circuits Conference, Hangzhou, China, 2006: 291-294. doi: 10.1109/ASSCC.2006.357908.
    WEY I C, LAN Y J, and PEND C. Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design[J]. Microelectronics Reliability, 2013, 53(12): 2057-2069.
    XIAO R and CHEN C. Power optimization design for probabilistic logic circuits[C]. IEEE International Symposium on Circuits and Systems, Lisbon, 2015: 2593-2595. doi: 10.1109/ISCAS.2015.7169216.
    KORKMAZ P and PALEM K V. Energy, performance, and probability tradeoffs for energy-efficient probabilistic CMOS circuits[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2008, 55(8): 2249-2262. doi: 10.1109/TCSI. 2008.920139.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (1006) PDF downloads(322) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return