Citation: | YE Yong, KANG Yong, SONG Zhitang, CHEN Bangming. Design of High-density Mask ROM Based on Diode Cells[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1452-1457. doi: 10.11999/JEIT160938 |
LU S K, TSAI C J, and HASHIZUME M. Enhanced built-in self-repair techniques for improving fabrication yield and reliability of embedded memories[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8): 2726-2734. doi: 10.1109/TVLSI.2016.2523499.
|
MOHAMMAD B S, SALEH H, and ISMAI M. Design methodologies for yield enhancement and power efficiency in SRAM-based SoCs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(10): 2054-2064. doi: 10.1109/TVLSI.2014.2360319.
|
CHEN Y J, HUANG C E, CHEN H M, et al. A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology[J]. IEEE Electron Device Letters, 2008, 29(8): 938-940. doi: 10.1109/LED.2008.2000969.
|
顾明, 杨军. 基于物理指数MOSFET模型的SRAM存储体单元优化[J]. 电子与信息学报, 2007, 29(1): 223-226.
|
GU M and YANG J. Optimization of SRAM memory cell based on physical alpha-power law MOSEFT model[J]. Journal of Electronics Information Technology, 2007, 29(1): 223-226.
|
KHANDELWAL S, RAJ B, and GUPTA R D. FinFET based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect[J]. Journal of Computational and Theoretical Nanoscience, 2015, 12(9): 2500-2506. doi: 10.1166/jctn.2015.4055.
|
WANG J, WANG L, YIN H, et al. cNV SRAM: CMOS technology compatible non-volatile SRAM based ultra-low leakage energy hybrid memory system[J]. IEEE Transactions on Computers, 2016, 65(4): 1055-1067. doi: 10.1109/TC. 2014.2375187.
|
NARUSE M, KAMEI T, KUNIO T, et al. A 65 nm single- chip application and dual-mode baseband processor with partial clock activation and IP-MMU[J]. IEEE Journal of Solid-State Circuits, 2009, 44(1): 83-89. doi: 10.1109/JSSC. 2008.2007169.
|
KULKARNI S H, CHEN Z, HE J, et al. A 4 kb metal-fuse OTP-ROM macro featuring a 2V programmable 1.37 m2 1T1R bit cell in 32 nm high-k metal-gate CMOS[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 863-868. doi: 10.1109/JSSC.2010.2040115.
|
LIU Z, ZHENG R, and SUN J. A gate-oxide-breakdown antifuse OTP ROM array based on TSMC 90 nm process[C]. 2015 International Symposium on Next-Generation Electronics (ISNE), Taipei, China, 2015: 1-3. doi: 10.1109/ ISNE.2015.7132015.
|
KULKARNI S H, CHEN Z, SRINIVASAN B, et al. A high- density metal-fuse technology featuring a 1.6 V programmable low-voltage bit cell with integrated 1 V charge pumps in 22 nm tri-gate CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(4): 1003-1008. doi: 10.1109/ JSSC.2015.2507786.
|
CHANG M F and YANG S M. Analysis and reduction of supply noise uctuations induced by embedded via- programming ROM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(6): 758-769. doi: 10.1109/TVLSI.2008.2006794.
|
JANG B J, LEE C H, SIM S H, et al. Robust via- programmable ROM design based on 45 nm process considering process variation and enhancement Vmin and yield[C]. IEEE International Symposium on Circuits and Systems (ISCAS), Piscataway, USA, 2015: 2541-2544. doi: 10.1109/ISCAS.2015.7169203.
|
UMEMOTO Y, NII Y, ISHIKAWA J, et al. 28 nm 50% power-reducing contacted mask read only memory macro with 0.72 ns read access time using 2T pair bitcell and dynamic column source bias control technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(3): 575-584. doi: 10.1109/TVLSI.2013.2246201.
|
HUANG C E, CHEN Y J, LAI H C, et al. A study of self- aligned nitride erasable OTP cell by 45-nm CMOS fully compatible process[J]. IEEE Transactions on Electron Device, 2009, 56(6): 1228-1234. doi: 10.1109/TED.2009.2018169.
|
YANG S M, CHANG M F, CHIANG C C, et al. Low-voltage embedded NAND-ROM macros using data-aware sensing reference scheme for VDDmin, speed and power improvement [J]. IEEE Journal of Solid-State Circuits, 2013, 48(2): 611-623. doi: 10.1109/JSSC.2012.2229068.
|
CHANG M F, YANG S M, LIANG C W, et al. Noise-immune embedded NAND ROM using a dynamic split source-line scheme for VDDmin and speed improvements[J]. IEEE Journal of Solid-State Circuits, 2010, 45(10): 2142-2155. doi: 10.1109/JSSC.2010.2060279.
|