Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology

HUANG Zhengfeng; WANG Shichao; OUYANG Yiming; YI Maoxiang; LIANG Huaguo

doi:10.11999/JEIT160889

Volume 39 Issue 6

Jun. 2017

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Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(6): 1464-1471

HUANG Zhengfeng, WANG Shichao, OUYANG Yiming, YI Maoxiang, LIANG Huaguo. Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889

Citation:

HUANG Zhengfeng, WANG Shichao, OUYANG Yiming, YI Maoxiang, LIANG Huaguo. Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889

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Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology

doi: 10.11999/JEIT160889

1.
(School of Electronic Science &
2.
(School of Computer &

Funds:

The National Natural Science Foundation of China (61574052, 61371025, 61474036, 61674048), The Natural Science Foundation of Anhui Province (1608085MF149)

Received Date: 2016-09-02
Rev Recd Date: 2017-02-22
Publish Date: 2017-06-19

Abstract

Abstract

To reduce the soft error rate of the circuit, this paper proposes a low power soft error tolerant latch based on time redundancy technology. The proposed latch can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes. Furthermore, it can efficiently mask the input Single Event Transient (SET). Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the proposed latch can be applied to clock-gating circuits. Detailed SPICE simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures. Compared with other soft error tolerant latches, the proposed latch introduces 13.4% delay overhead on average. While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP), and 9.1% reduction in transistor numbers on average.
- Soft error,
- Single Event Upset (SEU),
- Single Event Transient (SET),
- Hardened latch

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References(26)

References

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