Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops

SHI Zhan; YU Jun; TANG Zhen’an; CAI Hong; FENG Chong

doi:10.11999/JEIT160826

Volume 39 Issue 6

Jun. 2017

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SHI Zhan, YU Jun, TANG Zhen’an, CAI Hong, FENG Chong. Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1472-1478. doi: 10.11999/JEIT160826

Citation:

SHI Zhan, YU Jun, TANG Zhen’an, CAI Hong, FENG Chong. Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1472-1478. doi: 10.11999/JEIT160826

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Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops

doi: 10.11999/JEIT160826

1.
(School of Electronic Science and Technology, Dalian University of Technology, Dalian 116024, China)
2.

Funds:

The National Natural Science Foundation of China (61131004, 61274076, 61001054)

Received Date: 2016-08-03
Rev Recd Date: 2017-02-08
Publish Date: 2017-06-19

Abstract

Abstract

On the basis of the analysis of the structure, operation principle and mechanism of generating spurs of the charge pump, a charge pump with a low static current mismatch and a low timing mismatch is proposed. This charge pump suppresses the jitter and spurs in high-speed Phase-Looked Loops (PLL) by improving the timing mismatch and the current mismatch during switching in the charge pump. Based on the SMIC 0.18 m CMOS radio frequency technology with 1.8 V power supply, the phase noise simulation of the PLLs adopting the proposed charge pump is performed. The simulation results demonstrate that those PLLs achieve a low noise performance: the second-order PLL shows a period jitter of 1.05 ps and the largest reference spur of -121 dBc with the PLL output frequency of 480 MHz.
- Integrated Circuits (IC),
- Phase-Locked Loop (PLL),
- Jitter,
- Reference spur

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References(31)

References

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