Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function

DAI Zibin; WANG Zhouchuang; LI Wei; LI Jiamin; Nan Longmei

doi:10.11999/JEIT160733

Volume 39 Issue 5

May 2017

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Article Navigation > Journal of Electronics & Information Technology > 2017 > 39(5): 1226-1232

DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733

Citation:

DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733

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Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function

doi: 10.11999/JEIT160733

1.
(The PLA Information Engineering University, Zhengzhou 450001, China)
2.
(State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China)

Funds:

The National Natural Science Foundation of China (61404175)

Received Date: 2016-07-08
Rev Recd Date: 2016-12-12
Publish Date: 2017-05-19

Abstract

Abstract

In order to solve the problem that the Non-Linear Boolean Function (NLBF) unit in sequence cryptogram possesses poor hardware resource utilization, the utilization model of basic component composed by Look-Up Table (LUT) is studied and three essential parameters (LUT size, cluster scale and the number of input ports) which impact hardware utilization are decided combined with the early processing results of adaption algorithm. On the basis, the mapping of NLBF limited to variable frequency is realized and the design of nonlinear computing unit is implemented, which can support multi-way parallel processing. The circuit is developed and synthesized in SMIC 180 nm. Its working frequency realizes 241 MHz and it achieves the maximum throughput of 7.71 Gb/s in parallelism of 32. The results after evaluating the utilization of various NLBFs show that all utilization can reach over 91.14% and the utilization increases continually as the parallelism increases.
- Sequence cryptogram,
- Reconfigurable computing,
- Non-Linear Boolean Function (NLBF),
- Look-Up Table (LUT)

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References(26)

References

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