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Volume 39 Issue 4
Apr.  2017
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LI Xiangcheng, CHEN Haiqiang, LIANG Qi, SUN Youming, WAN Haibin, QIN Tuanfa. Binary Decoding Message Iterative Majority-logic LDPC Decoding and Its Quantizing Optimization[J]. Journal of Electronics & Information Technology, 2017, 39(4): 873-880. doi: 10.11999/JEIT160563
Citation: LI Xiangcheng, CHEN Haiqiang, LIANG Qi, SUN Youming, WAN Haibin, QIN Tuanfa. Binary Decoding Message Iterative Majority-logic LDPC Decoding and Its Quantizing Optimization[J]. Journal of Electronics & Information Technology, 2017, 39(4): 873-880. doi: 10.11999/JEIT160563

Binary Decoding Message Iterative Majority-logic LDPC Decoding and Its Quantizing Optimization

doi: 10.11999/JEIT160563
Funds:

The National Natural Science Foundation of China (61261023, 61362010, 61661005), The Natural Science Foundation of Guangxi (2014GXNSFBA118276)

  • Received Date: 2016-06-01
  • Rev Recd Date: 2016-11-25
  • Publish Date: 2017-04-19
  • A low complexity iterative majority-logic decoding algorithm is presented. For the presented algorithm, binary decoding messages are involved in the message passing, processing and updating process. Instead of computing the extrinsic information, the presented algorithm computes the reliability measure based on syndrome states (correct or error) in the Tanner graph. Compared with several existing iterative majority-logic decoding algorithms, the presented algorithm does not require the information scaling and hence can avoid the corresponding real multiplication operations. This leads to very low decoding complexity. Furthermore, a special quantization is combined with the presented algorithm. The optimization method is also given based on the discrete Density Evolution (DE). Simulation results show that, compared with the original algorithm, the presented algorithm can achieve about 0.3~0.4 dB performance gain over the Additive White Gaussian Noise (AWGN) channel. Moreover, all the decoding messages exchanged among the nodes are binary-based, which makes the presented algorithm convenient for the hardware implementations.
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