An Ultra-high-speed Fully-parallel Fast Fourier Transform Design

CHEN Jienan; FEI Chao; YUAN Jiansheng; ZENG Weiqi; LU Hao; HU Jianhao

doi:10.11999/JEIT160036

Volume 38 Issue 9

Sep. 2016

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Article Navigation > Journal of Electronics & Information Technology > 2016 > 38(9): 2410-2414

CHEN Jienan, FEI Chao, YUAN Jiansheng, ZENG Weiqi, LU Hao, HU Jianhao. An Ultra-high-speed Fully-parallel Fast Fourier Transform Design[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036

Citation:

CHEN Jienan, FEI Chao, YUAN Jiansheng, ZENG Weiqi, LU Hao, HU Jianhao. An Ultra-high-speed Fully-parallel Fast Fourier Transform Design[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036

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An Ultra-high-speed Fully-parallel Fast Fourier Transform Design

doi: 10.11999/JEIT160036

Funds:

The National Natural Science Foundation of China (6150010678, 61371104)

Received Date: 2016-01-13
Rev Recd Date: 2016-05-30
Publish Date: 2016-09-19

Abstract

Abstract

The design and implementation of ultra-high-speed FFT processor is imperative in radar system and prospective wireless communication system. In this paper, the fully-parallel-architecture FFT with bit-serial arithmetic is proposed. This method avoids the complexity of data addressing, access and routing. Based on the high-radix factorization, the multiplication number can be reduced. Out of the reason that twiddle factors are fixed in the design, constant coefficient optimization can be used in multiplications. Besides, bit-serial arithmetic cuts down the hardware cost, and makes the computation elements full-load to get a 100% efficiency. As a result, the presented 512-point FFT processer has 5.97 times gain in speed-throughput ratio while its hardware only accounts for 30% LUTs and 9% registers resource based on Xilinx V7-980t FPGA.
- Fast Fourier Transform (FFT),
- Full parallel,
- Bit-serial calculation,
- Constant coefficient multiplication

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References(16)

References

霍凯, 赵晶晶. OFDM新体制雷达研究现状与发展趋势[J]. 电子与信息学报, 2015, 37(11): 2776-2789. doi: 10.11999/ JEIT150335.

HUO Kai and ZHAO Jinjin. The development and prospect of the new OFDM radar[J]. Journal of Electronics Information Technology, 2015, 37(11): 2776-2789. doi: 10. 11999/JEIT150335.

张洪伦, 巴晓辉, 陈杰, 等. 基于FFT的微弱GPS信号频率精细估计[J]. 电子与信息学报, 2015, 37(9): 2132-2137. doi: 10.11999/JEIT150204.

ZHANG Honglun, BA Xiaohui, CHEN Jie, et al. FFT-based fine frequency estimation for weak GPS signal[J]. Journal of Electronics Information Technology, 2015, 37(9): 2132-2137. doi: 10.11999/JEIT150204.

罗亚松, 许江湖, 胡洪宁, 等. 正交频分复用传输速率最大化自适应水声通信算法研究[J]. 电子与信息学报, 2015, 37(12): 2872-2876. doi: 10.11999/JEIT150440.

LUO Yasong, XU Jianghu, HU Hongning, et al. Research on self-adjusting OFDM underwater acoustic communication algorithm for transmission rate maximization[J]. Journal of Electronics Information Technology, 2015, 37(12): 2872-2876. doi: 10.11999/JEIT150440.

WANG Chao, YAN Yuwei, and FU Xiaoyu. A high- throughput low-complexity radix-24-22-23 FFT/IFFT processor with parallel and normal input/output order for IEEE 802.11ad systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015, 23(11): 2728-2732. doi: 10.1109/TVLSI.2014.2365586.

YU Chu and YEN Mao-Hsu. Area-efficient 128-to 2048/ 1536-point pipeline FFT processor for LTE and mobile WiMAX systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2014, 23(9): 1793-1800. doi: 10.1109/ TVLSI.2014.2350017.

WANG Zeke, LIU Xue, HE Bingsheng, et al. A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT[J]. IEEE Transactions on Very Large Scale Integration Systems, 2014, 23(5): 973-977. doi: 10.1109/TVLSI.2014. 2319335.

CHEN Jienan, Hu Jianhao, and LEE Shuyang. High throughput and hardware efficient FFT architecture for LTE application[C]. IEEE Wireless Communications Networking Conference. Shanghai, 2012: 826-831. doi: 10.1109/WCNC.2012.6214486.

CHEN Jienan, HU Jianhao, LEE Shuyang, et al. Hardware efficient mixed radix-25/16/9 FFT for LTE systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015, 23(2): 221-229. doi: 10.1109/TVLSI.2014.2304834.

COOLEY J W and TUKEY J W. An algorithm for the machine calculation of complex Fourier series[J]. Mathematics of Computation, 1965, 19(90): 297-301. doi: 10.2307/2003354.

DUHAMEL P and VETTERLI M. Fast fourier transforms: a tutorial review and a state of the art[J]. Signal Processing, 1990, 19(4): 259-299. doi: 10.1016/0165-1684(90)90158-U.

YANG Lang and CHEN T W. A low power 64-point bit-serial FFT engine for implantable biomedical applications[C]. Euromicro Conference on Digital System Design, Funchal, Portugal, 2015: 383-389. doi: 10.1109/DSD.2015.30.

PARHI K K. VLSI Digital Signal Processing Systems: Design and Implementation[M]. New York, USA, John Wiley Sons, 1999: 490-499.

MA Zhenguo, YIN Xiaobo, and YU Feng. A novel memory-based FFT architecture for real-valued signals based on radix-2 decimation-in-frequency algorithm[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2015, 62(9): 876-880. doi: 10.1109/TCSII.2015.2435522.

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