Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen

CUI Xiaoping; WANG Shumin; LIU Weiqiang; DONG Wenwen

doi:10.11999/JEIT151416

Volume 38 Issue 10

Oct. 2016

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CUI Xiaoping, WANG Shumin, LIU Weiqiang, DONG Wenwen. Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen[J]. Journal of Electronics & Information Technology, 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416

Citation:

CUI Xiaoping, WANG Shumin, LIU Weiqiang, DONG Wenwen. Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen[J]. Journal of Electronics & Information Technology, 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416

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Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen

doi: 10.11999/JEIT151416

Received Date: 2015-12-14
Rev Recd Date: 2016-06-08
Publish Date: 2016-10-19

Abstract

Abstract

There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.
- Decimal addition,
- Conditional speculative decimal addition,
- Parallel prefix,
- Carry select adder

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References(18)

References

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