An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA

HUANG Zhihong; LI Wei; YANG Liqun; JIANG Zhenghong; WEI Xing; LIN Yu; YANG Haigang

doi:10.11999/JEIT151216

Volume 38 Issue 9

Sep. 2016

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Article Navigation > Journal of Electronics & Information Technology > 2016 > 38(9): 2397-2404

HUANG Zhihong, LI Wei, YANG Liqun, JIANG Zhenghong, WEI Xing, LIN Yu, YANG Haigang. An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2397-2404. doi: 10.11999/JEIT151216

Citation:

HUANG Zhihong, LI Wei, YANG Liqun, JIANG Zhenghong, WEI Xing, LIN Yu, YANG Haigang. An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2397-2404. doi: 10.11999/JEIT151216

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An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA

doi: 10.11999/JEIT151216

1.
2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61271149)

Received Date: 2015-10-28
Rev Recd Date: 2016-03-04
Publish Date: 2016-09-19

Abstract

Abstract

In order to break through the bottleneck of the huge cluster area in AIC (And-Inverter Cone) architecture based FPGA, the research on the optimisation of the input crossbar architecture is carried on. A post-pack netlist statistics method is creatively proposed to analyze the utilization of AIC cluster inputs and feedbacks and to guide the input crossbar design. And on the architecture parameter design level, it is firstly proposed to separately design the connective probability of the AIC cluster inputs and feedbacks. Through substantial experiments, optimum connective probability combination is derived. From the circuit implement view, dual-phases multiplexer input crossbar is presented according to the characteristics of AIC. The area of the AIC cluster, optimized through the proposed approach, achieves 21.21% smaller than the original one, the huge area problem is markedly ameliorated. When implementing the MCNC and VTR benchmarks, compared to Stratix IV, LUT based FPGA from Altera, the area-delay product of the AIC FPGA after optimisation is reduced by 48.49% and 26.29%, respectively. Compared to the original AIC-based FPGA architecture, the area-delay product is reduced by 28.48% and 28.37%, respectively.
- And-Inverter Cone (AIC),
- AIC cluster,
- Post-pack netlist statistics,
- Connective probability,
- Separately design

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References(19)

References

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