Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

Huang Zhi-hong; Yang Hai-gang; Yang Li-qun; Li Wei; Jiang Zheng-hong; Lin Yu

doi:10.11999/JEIT150249

Volume 37 Issue 12

Jan. 2016

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Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249

Citation:

Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249

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Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

doi: 10.11999/JEIT150249

1.
2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61271149)

Received Date: 2015-02-12
Rev Recd Date: 2015-09-16
Publish Date: 2015-12-19

Abstract

Abstract

With deep understanding of the characteristics of And-Inverter Cone (AIC), an alternative logic element for FPGA, a series of improvements are proposed to get an optimized interconnect architecture inside the logic cluster. The enhancements include removing the output crossbar, adopting Inverter-Suffixed Crossbar (ISC), optimizing the low load circuit path, dividing the feedback and output function, restricting the output level of AIC and removing the middle crossbar, mixing with the LUT element. An optimized architecture is derived through amounts of experiments. Compared to Stratix IV, Altera, the area of cluster is reduced by 9.06%.Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 40.82%; the average area-delay product of VTR benchmarks is reduced by 17.38%. Compared to the original AIC-based FPGA architecture, the area of AIC cluster is reduced by 23.16%. Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 27.15%; the average area-delay product of VTR benchmarks are reduced by 15.26%.
- And-Inverter Cone (AIC),
- AIC cluster,
- Inverter-Suffixed Crossbar (ISC),
- Cluster interconnect architecture

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References(16)

References

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