Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration

Yang Li-qun; Li Wei; Huang Zhi-hong; Sun Jia-bin; Yang Hai-gang

doi:10.11999/JEIT150162

Volume 37 Issue 10

Sep. 2015

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Article Navigation > Journal of Electronics & Information Technology > 2015 > 37(10): 2521-2528

Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang. Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162

Citation:

Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang. Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162

Citation:

Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang. Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162

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Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration

doi: 10.11999/JEIT150162

1.
2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61271149)

Received Date: 2015-01-28
Rev Recd Date: 2015-04-22
Publish Date: 2015-10-19

Abstract

Abstract

A circuit characteristics-driven semi-supervised modelling approach is proposed for FPGA architecture design space exploration. By including circuit characteristics as input, the proposed approach can estimate the performance of specific circuit on certain architecture accurately. Experimental results illustrate that the approach estimates the area with Mean Relative Error (MRE) up to 6.25%, and delay up to 4.23%, which is comparable to the Semi-supervised Model Tree (SMT) approach. Meanwhile, the proposed approach speedups the modelling process. Compared to the SMT approach, the proposed approach reduces the time cost from 500 h to 250 h when exploring a design space with millions of architectures inside on Intel Xeon E7-4807 platform.
- FPGA design space,
- Semi-supervised modelling approach,
- Circuit characteristics

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References(16)

References

Luu J, Goeders J, Wainberg M, et al.. VTR 7.0: next generation architecture and CAD system for FPGAs[J]. ACM Transactions on Reconfigurable Technology and Systems, 2014, 7(2): 6:1-6:30.

Marquardt A, Betz V, and Rose J. Speed and area tradeoffs in cluster-based FPGA architectures[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(1): 84-93.

Ahmed E and Rose J. The effect of LUT and cluster size on deep-submicron FPGA performance and density[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(3): 288-298.

Jiang Zheng-hong, Lin C Y, Yang Li-qun, et al.. Exploring architecture parameters for dual-output LUT based FPGAs[C]. Proceedings of the 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, 2014: 1-6.

Betz V, Rose J, and Marquardt A. Architecture and CAD for Deep-Submicron FPGAs [M]. Netherlands, Kluwer Academic Publishers, 1999: 15-20.

Gao Hai-xia, Yang Yin-tang, Ma Xiao-hua, et al.. Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations[C]. Proceedings of the 6th International Symposium on Quality of Electronic Design, San Jose, CA, USA, 2005: 370-374.

Smith A, Wilton S, and Das J. Wirelength modeling for homogeneous and heterogeneous FPGA architectural development[C]. Proceedings of the 17th ACM/SIGDA international symposium on Field programmable gate arrays, Monterey, CA, USA, 2009: 181-190.

Das J, Lam A, Wilton S, et al.. An analytical model relating FPGA architecture to logic density and depth[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(12): 2229-2242.

Smith A, Constantinides G, and Cheung P. FPGA architecture optimization using geometric programming[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(8): 1163-1176.

Pandurangaiah Y, Reddy V, and Chakravarthy K. Area-delay estimation by concurrent optimization of FPGA architecture parameters using geometric programming[J]. International Journal of Computer Applications, 2013, 82(18): 4-11.

Mehri H and Alizadeh B. An analytical dynamic and leakage power model for FPGAs[C]. Proceedings of the 22nd Iranian Conference on Electrical Engineering (ICEE), Tehran, 2014: 300-305.

Leow Yoon-kah. Post-routing analytical models for homogeneous FPGA architectures[D]. [Ph. D. dissertation], The University of Arizona, 2013.

Yang Li-qun, Yang Hai-gang, Li Wei, et al.. A semi-supervised modeling approach for performance characterization of FPGA architectures[C]. Proceedings of the 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, 2014: 1-6.

Wang Y and Witten I H. Inducing model trees for continuous classes[C]. Proceedings of the Ninth European Conference on Machine Learning, Prague, Czech Republic, 1997: 128-137.

Brayton R and Mishchenko A. ABC: an academic industrial-strength verification tool[J]. Computer Aided Verification, 2010, 6174: 24-40.

Zgheib G, Yang Li-qun, Huang Zhi-hong, et al.. Revisiting and-inverter cones[C]. Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 2014: 45-54.

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