Mapper for AIC-based FPGAs

Jiang Zheng-hong; Lin Yu; Huang Zhi-hong; Yang Li-qun; Yang Hai-gang

doi:10.11999/JEIT141403

Volume 37 Issue 7

Jul. 2015

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2015 > 37(7): 1769-1773

Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. Journal of Electronics & Information Technology, 2015, 37(7): 1769-1773. doi: 10.11999/JEIT141403

Citation:

Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. Journal of Electronics & Information Technology, 2015, 37(7): 1769-1773. doi: 10.11999/JEIT141403

Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. Journal of Electronics & Information Technology, 2015, 37(7): 1769-1773. doi: 10.11999/JEIT141403

Citation:

PDF( 673 KB)

Mapper for AIC-based FPGAs

doi: 10.11999/JEIT141403

1.
2.
(System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Received Date: 2014-11-20
Rev Recd Date: 2015-03-16
Publish Date: 2015-07-19

Abstract

Abstract

Exploring a new logic element of Field Programmable Gate Array (FPGA) is always a key field in FPGAs research, while And-Inverter Cones (AIC) is the most promising one. Implementing a highly-efficient and highly-flexible mapping tool is also an important part of exploring new FPGA architecture. In this paper, a new mapper for AIC-based FPGA is implemented. Compared with an existing mapper, the new mapper has much higher flexibility, and supports adjustments of AICs architectural parameters to assit the design space exploration of AIC. Meanwhile, the new mapper provides area results 33%~36% better than the original mapper.
- Field Programmable Gate Array (FPGA),
- And-Inverter Cones (AIC),
- Technology mapping

FullText(HTML)

References(13)

References

Ian K and Rose J. Measuring the gap between FPGAs and ASICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(2): 271-285.

Ngai T, Rose J, and Wilton S. An SRAM programmable field-configurable memory[C]. Proceedings of the IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1995: 499-502.

Rui Jia, Lin Y, Guo Z, et al.. A survey of open source processors for FPGAs[C].?IEEE International Conference on Field Programmable Logic and Applications (FPL), Munich, 2014: 521-526.

Hutton M, Schleicher J, Lewis D, et al.. Improving FPGA performance and area using an adaptive logic module [C].?IEEE International Conference on Field Programmable Logic and Applications (FPL), Belgium, 2004: 135-144.

Lewis D, Ahmed E, Baeckler G, et al.. The stratix II logic and routing architecture[C]. Proceedings of the 2005 ACM/ SIGDA 13th ACM International Symposium on Field- Programmable Gate Grrays, Monterey, 2005: 14-20.

Jiang Z, Lin Y, Yang L, et al.. Exploring architecture parameters for dual-output LUT based FPGAs[C]. IEEE International Conference on Field Programmable Logic and Applications (FPL), Munich, 2014: 436-441.

Parandeh-Afshar H, Benbihi H, Novo D, et al.. Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones[C]. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, 2012: 119-128.

Parandeh-Afshar H, Zgheib G, Novo D, et al.. Shadow and-inverter cones[C]. IEEE International Conference on Field Programmable Logic and Applications (FPL), Porto, 2013: 1-4.

Zgheib G, Yang L, Huang Z, et al.. Revisiting and-inverter cones[C]. Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM, Monterey, 2014: 45-54.

Brayton R and Mishchenko A. ABC: an academic industrial- strength verification tool[C]. Computer Aided Verification, Edinburgh, 2010: 24-40.

Mishchenko A,? Cho S, Chatterjee S, et al.. Combinational and sequential mapping with priority cuts[C].?IEEE International Conference on Computer-Aided Design, San Jose, 2007: 354-361.

Cong J, Wu C, and Ding Y. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution [C].?Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Grrays, Monterey, 1999: 29-35.

Luu J,? Goeders J, Wainberg M, et al.. VTR 7.0: Next generation architecture and CAD system for FPGAs[J]. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2014,?7(2): DOI: 10.1145/2617593.

Relative Articles

Supplements(0)

Cited By

Proportional views