DSC-PUF：抗机器学习攻击的动态空间耦合强PUF电路

胡双; 汪鹏君; 周桢凯; 张跃军; 方震

doi:10.11999/JEIT261012

DSC-PUF：抗机器学习攻击的动态空间耦合强PUF电路

doi: 10.11999/JEIT261012 cstr: 32379.14.JEIT261012

胡双^1,,
汪鹏君^2, ,,
周桢凯¹,
张跃军¹,
方震¹

1.
宁波大学集成电路学院宁波 315211
2.
温州大学电气与电子工程学院温州 325035

基金项目: 国家自然科学基金(62234008, 62474100)，浙江省“尖兵领雁+X”科技计划项目(2025C01063)，宁波市科创甬江2035重点研发计划(2024Z139)

详细信息

作者简介:
胡双：胡双：女，博士生，研究方向为抗机器学习攻击的物理不可克隆电路设计，　2501100064@nbu.edu.cn

汪鹏君：男，教授，研究方向为集成电路设计、信息安全等技术及相关理论，　wangpengjun@wzu.edu.cn

周桢凯：男，硕士生，研究方向为高可靠物理不可克隆电路设计

张跃军：男，教授，研究方向为低功耗、高信息密度集成电路理论和设计

方震：男，硕士生，研究方向为高安全物理不可克隆电路设计

通讯作者:
汪鹏君　wangpengjun@wzu.edu.cn

中图分类号: TN47; TN402
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出版历程
- 修回日期: 2026-10-16
- 录用日期: 2026-10-16
- 网络出版日期: 2026-10-29

DSC-PUF: Dynamic Spatial Coupling Strong PUF Circuit Against Machine Learning Attacks

1.
School of Integrated Circuits, Ningbo University, Ningbo 315211, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Funds: The National Natural Science Foundation of China (62234008, 62474100), The Zhejiang Provincial Science and Technology Program “Pioneer and Leading Goose + X” Project (2025C01063), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139)

摘要

摘要: 物理不可克隆函数(Physical Unclonable Function, PUF)作为物联网设备身份认证的关键安全原语，但其实际应用场景中也面临机器学习攻击威胁。针对传统延时型强PUF底层结构存在的线性相关特性与安全隐患问题，提出一种动态空间耦合的强PUF(Dynamic Spatial Coupling Strong PUF, DSC-PUF)电路。首先采用主从双链协同结构，其中主链作为物理熵源，通过内部延时竞争过程提取不可预测的隐藏状态，从链用于生成响应。其次，设计动态空间耦合网络(Dynamic Spatial Coupling Network, DSCN)模块，利用隐藏状态作为动态控制信息，对输入挑战进行掩码调制、大跨度移位扩散以及对称交织异或等多级空间耦合操作，将动态耦合后的挑战输入从链生成响应，最终将双链路响应异或，进一步增强输出序列的非线性特征，提升抗机器学习攻击能力。最后，在Xilinx Artix-7 FPGA中实现电路并测试，结果表明，DSC-PUF面对逻辑回归、支持向量机、人工神经网络等典型机器学习攻击时的预测准确率均显著下降，预测率在50.28%至53.39%之间,同时，在–40 ℃至80 ℃的温度范围内，最低可靠性为98.49%，严格雪崩准则均值约为0.517，唯一性和自相关性分别为0.5152和0.0141，且通过NIST800-22随机性测试。
- 硬件安全 /
- 物理不可克隆函数 /
- 抗机器学习攻击 /
- 动态空间耦合网络 /
- 严格雪崩准则
Abstract: Objective The large-scale deployment of Internet of Things (IoT) devices raises the demand for lightweight authentication and dynamic key generation on resource-limited hardware. Physical Unclonable Functions (PUFs) leverage inherent manufacturing variations of integrated circuits to generate unique, unclonable hardware fingerprints, serving as an effective lightweight scheme for device authentication and secure key derivation. Nevertheless, conventional delay-based strong PUFs feature linear delay superposition, rendering their challenge–response relationships susceptible to machine learning modeling. Existing countermeasures against modeling attacks enhance nonlinearity using elaborate feedback loops, multi-stage XOR gates and heterogeneous logic cells. Though these approaches improve security to some extent, they incur substantial hardware overhead, timing convergence problems, degraded reliability and weak environmental robustness. This work presents a Dynamic Spatial Coupling Strong PUF (DSC-PUF) architecture. With restrained hardware cost, the proposed design maintains PUFs’ inherent physical properties and resistance to machine learning attacks, enabling joint optimization of multi-dimensional system metrics. Methods To mitigate modeling vulnerabilities of conventional strong PUFs and resolve the tradeoff between security and reliability, this paper presents a DSC-PUF architecture with dual delay chains and dynamic spatial perturbation. It consists of a primary chain A, an auxiliary chain B, and a dynamic spatial coupling network. As signals propagate, the primary chain captures multi-level delay competition outcomes to produce random hidden states governed by physical process variations. Using these hidden states as dynamic control signals, nonlinear transformations including mask modulation, long-range shift diffusion, and symmetric interleaved XOR are applied to input challenges. This dynamically varies the challenge space seen by the auxiliary chain and breaks the stable linear CRP mapping inherent in traditional PUFs. To suppress dynamic interference to system stability, a master-slave asynchronous triggering mechanism is introduced. It temporally isolates hidden state latching, spatial coupling and auxiliary-chain propagation to prevent glitch propagation and race hazards. A majority voting scheme is also utilized for response denoising to enhance output robustness under harsh operating conditions. Results and Discussions The proposed architecture was implemented on a Xilinx Artix-7 FPGA platform, and its performance was evaluated through multiple standard tests. Experimental results demonstrate that the DSC-PUF significantly enhances the resistance of conventional delay-based PUFs against machine learning modeling attacks. Under typical attacks, including Logistic Regression, Support Vector Machine, Deep Neural Network, Covariance Matrix Adaptation Evolution Strategy, Convolutional Neural Network, and Light Gradient Boosting Machine, the prediction accuracy remains between 50.28% and 53.39%, close to the random-guessing level (Fig. 5), indicating that the dynamic spatial reconfiguration mechanism effectively disrupts the stable feature distribution of conventional CRPs. The proposed structure has a minimum reliability of 98.49% in the temperature range of -40℃ to 80℃, satisfying the reliability requirements of IoT devices in complex environments (Fig. 6). The generated responses successfully passed the NIST SP800-22 randomness test suite (Table 1 and Fig. 7), while the autocorrelation coefficients remained within the 95% confidence bounds of ±0.0141 (Fig. 8), demonstrating favorable randomness and low data correlation. In addition, the proposed architecture achieved a uniqueness value of 0.5152 and an average Strict Avalanche Criterion value of approximately 0.517 (Fig. 9 and 10), both close to the theoretical ideal values. The hardware overhead of the proposed design is 606 LUTs and 350 FFs (Table 2), demonstrating good lightweight implementation efficiency. Compared with existing strong PUF structures, the proposed DSC-PUF achieves a better balance among attack resistance, reliability, randomness, and hardware overhead. Conclusions This paper proposes a dynamic spatial coupling strong PUF architecture with enhanced resistance against machine learning attacks. By introducing a hidden-state-driven dynamic spatial coupling mechanism, the proposed architecture dynamically reconstructs challenge features, thereby disrupting the stable linear characteristics of conventional delay-based PUFs and reducing the statistical learnability of challenge–response mappings. Experimental results demonstrate that the DSC-PUF effectively resists LR, SVM, DNN, CMA-ES, CNN, and LightGBM modeling attacks, with prediction accuracies reduced to near-random guessing levels, while maintaining favorable reliability, randomness, uniqueness, and avalanche characteristics. This architecture provides a reliable hardware security solution for device authentication and secure key generation in resource-constrained IoT environments.
- Hardware Security /
- Physical Unclonable Function (PUF) /
- Resistance to Machine Learning Attacks /
- Dynamic Spatial Coupling Network (DSCN) /
- Strict Avalanche Criterion (SAC)

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图 1 APUF电路延时结构

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图 2 DSC-PUF总体架构

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图 3 动态空间耦合网络结构

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图 4 系统状态时序图

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图 5 机器学习模型预测率

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图 6 不同温度环境中PUF可靠性

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图 7 DSC-PUF响应分布图和灰度图

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图 8 自相关测试结果

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图 9 片间汉明距离

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图 10 严格雪崩准则测试

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1 DSCN挑战重构方式

输入：原始挑战$ \boldsymbol{C}\in\{{0,1}\}^{64} $和隐藏状态H=[H₃, H₂, H₁, H₀]
输出：重构挑战C_B
(1) 通过重复H生成动态掩码M
(2) for i = 0 to 63 do
(3) 　M[i] ← H[i mod 4]
(4) end for
(5) C_m ← C XOR M
(6) C_L← C_m << α
(7) C_R ← C_m >> β
(8) C_B ←C_m XOR C_L XOR C_R
(9) return C_B

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表 1 NIST随机性测试

测试项目	P-Value	通过/不通过
近似熵	1.00000	通过
块内频率	0.41847	通过
累加和	0.50253	通过
离散傅里叶变换	0.61809	通过
频率	0.47583	通过
线性复杂度	0.71981	通过
块内最长游程	0.52598	通过
非重叠模块匹配	0.60330	通过
串行	0.32630	通过
游程	0.45428	通过

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表 2 与相关文献性能对比

PUF类型	设计平台	预测率(%)	唯一性(%)	可靠性(%)	温度(℃)	结构数量(个)
BF PUF^[19]	Virtex-7	52.6	49.99	84.2	–10～80	405 LUTs
BF PUF^[19]	Virtex-7	52.6	49.99	84.2	–10～80	312 FFs
Ca PUF^[17]	Virtex-7	57	55.63	92.54	-	3290 LUTs
Ca PUF^[17]	Virtex-7	57	55.63	92.54	-	- FFs
PRO PUF^[20]	Spartan 6	72	44.79	98.01	–40～80	820 LUTs
PRO PUF^[20]	Spartan 6	72	44.79	98.01	–40～80	420 FFs
cSOI PUF^[24]	Artix-7	58.71	49.8	83	–20～80	1035 LUTs
cSOI PUF^[24]	Artix-7	58.71	49.8	83	–20～80	264 FFs
CT PUF^[18]	ZedBoard	60	49	96	–25～75	731 LUTs
CT PUF^[18]	ZedBoard	60	49	96	–25～75	486 FFs
本文	Artix-7	53.39	51.52	98.49	–40～80	606 LUTs
本文	Artix-7	53.39	51.52	98.49	–40～80	350 FFs

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