集成反向沟道的非对称阶梯式4H-SiC MOSFET

商世广; 贾苇; 魏佳蕊; 马锦涛; 陈庆

doi:10.11999/JEIT260907

集成反向沟道的非对称阶梯式4H-SiC MOSFET

doi: 10.11999/JEIT260907 cstr: 32379.14.JEIT260907

西安邮电大学电子工程学院西安 710121

基金项目: 陕西省重点研发计划项目(2026CY-YBXM-062)

详细信息

作者简介:
商世广：男，教授，研究方向为SGT MOSFET、SJ MOSFET、IGBT等半导体功率器件

贾苇：女，硕士研究生，研究方向为4H SiC MOSFET

魏佳蕊：女，硕士研究生，研究方向为Si MOSFET、Si IGBT

马锦涛：男，硕士研究生，研究方向为Si SGT MOSFET

陈庆：女，博士研究生，研究方向为宽禁带半导体材料与器件

通讯作者:
贾苇　13474028416@163.com

中图分类号: TN368.1
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出版历程
- 收稿日期: 2026-07-02
- 修回日期: 2026-09-29
- 录用日期: 2026-10-16
- 网络出版日期: 2026-10-22

Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel

School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China

Funds: Technology Project of Shaanxi Province, China (Grant Nos. 2026CY-YBXM-062)

摘要

摘要: 针对传统4H-SiC双沟槽MOSFET(Conventional Dual Trench MOSFET, CON-DTMOS)反向续流时寄生体二极管导通电压高、导通后易引发双极退化的性能缺陷，设计了一种集成平面-垂直沟道的4H-SiC双沟槽MOSFET(Lateral-Vertical Channel Dual Trench MOSFET, LV-DTMOS)，在此基础上引入内嵌反向沟道形成一种非对称阶梯式MOSFET(Reverse Channel Integrated Asymmetric Step MOSFET, RC-ASMOS)。RC-ASMOS以垂直沟道CH1和平面沟道CH2为正向导通沟道，不仅有效降低器件的导通电阻，优化器件静态特性，还可屏蔽器件的栅漏电容C_GD，使其动态特性显著提升；此外，引入的反向沟道CH3，可凭借较低的反向开启电压抑制体二极管的导通，避免体二极管的双极退化效应。仿真结果表明，相比CON-DTMOS，RC-ASMOS的比导通电阻R_on,sp降低29.1%，反向开启电压V_F降低42.9%，击穿电压BV提高36.5%，反向恢复电荷Q_RR减小46.2%，栅电荷Q_GD降低53.9%。因此RC-ASMOS兼具优异的静态性能与动态性能，这为其高频场景的应用打下了坚实的基础。
- MOSFET /
- 体二极管 /
- 接源栅 /
- 反向续流 /
- 双极退化
Abstract: Objective Featuring superior material properties including high thermal conductivity, high critical breakdown electric field, and high electron saturation velocity, 4H-SiC MOSFETs break through the performance bottlenecks of conventional silicon-based MOSFETs and satisfy the core requirements of power electronic systems for high frequency, miniaturization, and high efficiency. Among them, the double-trench 4H-SiC MOSFET (DT-MOS) developed by ROHM has been widely adopted in power electronic systems such as three-phase inverters for new energy vehicles and wind power generation. Nevertheless, the conventional DT-MOS (CON-DTMOS) suffers from prominent performance limitations. Restricted by the wide-bandgap characteristics of 4H-SiC materials, its parasitic body diode exhibits poor reverse freewheeling capability and high conduction loss, accompanied by severe bipolar degradation. In addition, the drawbacks of CON-DTMOS, including large on-resistance, high gate-drain capacitance, and excessive reverse recovery charge, further limit its application scope. To address the aforementioned performance deficiencies of CON-DTMOS, this paper proposes two novel device structures, namely LV-DTMOS and RC-ASMOS. By introducing planar channels and reverse channels, the proposed structures reduce the on-resistance and reverse turn-on voltage and effectively suppress the bipolar degradation induced by the body diode. Meanwhile, the optimized trench structure shields the gate-drain capacitance and improves the dynamic characteristics of the device. Consequently, the optimized 4H-SiC MOSFET with comprehensive and balanced performance is realized, which completely eliminates the bipolar degradation effect and lays a solid foundation for the reliable application of 4H-SiC MOSFETs in high-frequency power electronic scenarios. Methods This paper carries out device structure design and parameter optimization based on the Sentaurus TCAD simulation platform. Taking the conventional double-trench 4H-SiC MOSFET (CON-DTMOS) as the research baseline, a novel LV-DTMOS structure with integrated Lateral-Vertical channels is firstly designed. On this basis, an asymmetric stepped RC-ASMOS with embedded reverse channels is further proposed through structural optimization.The forward channels CH1 and CH2 can significantly reduce the on-resistance and improve the chip integration level. Moreover, the CH2 integrated at the trench bottom can shield the gate-drain coupling capacitance, thereby enhancing the dynamic performance of the device. Meanwhile, the embedded reverse channel CH3 can be turned on at a low reverse turn-on voltage through an ultra-thin oxide layer prior to the intrinsic body diode. This avoids the electron-hole recombination process and fundamentally eliminates the bipolar degradation effect.To improve the accuracy and reliability of simulation results, multiple critical physical models are adopted in the simulation process, including the incomplete ionization model, bandgap narrowing model, avalanche effect model, and high-field mobility saturation model. Furthermore, an interface charge model is introduced to account for the influence of interface state charges at the SiC/SiO₂ interface on channel mobility. The comprehensive application of the above multi-physical models enables the establishment of a simulation model that is highly consistent with the physical behaviors of practical devices, which provides a reliable support for subsequent device characteristic analysis and parameter optimization. Results and Discussions Simulation results indicate that the RC-ASMOS achieves optimal comprehensive performance under the structural and doping parameters of a CSL layer doping concentration of 4.5×10¹⁷ cm^–3, a reverse channel width of 0.35 μm, a source oxide thickness of 0.012 μm, and a P-body doping concentration of 2.0×10¹⁹ cm^–3. Compared with the conventional CON-DTMOS, the optimized RC-ASMOS exhibits substantial improvements in overall performance. The specific on-resistance of the RC-ASMOS is reduced by 29.1%, and the forward voltage drop is decreased from 2.8 V to 1.6 V, corresponding to a reduction of 42.9%. In addition, the proposed device effectively optimizes the internal electric field distribution and alleviates the electric field crowding effect, leading to a 36.5% enhancement in breakdown voltage (Fig. 11, Fig. 12). Benefiting from the CH2 integrated at the trench bottom, the gate-drain coupling effect is effectively weakened, which significantly reduces the gate-drain capacitance and lowers the gate charge by 53.9% (Fig. 13, Fig. 14. Furthermore, the RC-ASMOS realizes unipolar reverse freewheeling through the embedded reverse channel CH3, which suppresses the minority carrier storage effect and greatly improves the reverse recovery characteristics. The reverse recovery charge is reduced by 46.2%, and the peak reverse current is remarkably decreased (Fig. 15). Consequently, the proposed RC-ASMOS possesses excellent static conduction performance and high-frequency dynamic switching performance simultaneously. Conclusions Based on the conventional double-trench 4H-SiC MOSFET (CON-DTMOS), this paper conducts device design, parameter optimization, and performance verification using the Sentaurus TCAD simulation platform. Firstly, an LV-DTMOS structure with integrated planar-vertical channels is simulated. On this basis, structural optimization is further performed, and a novel RC-ASMOS device with embedded reverse channels is proposed. By optimizing the internal carrier transport paths, the RC-ASMOS achieves significant improvements in both static and dynamic device performance.Thanks to the unique reverse channel, the RC-ASMOS can be turned on for reverse freewheeling prior to the parasitic body diode, which avoids the internal electron-hole recombination process and fundamentally eliminates the bipolar degradation effect. Meanwhile, the RC-ASMOS remarkably reduces the gate-drain overlapping area, yielding a substantial improvement in dynamic characteristics. Overall, the proposed RC-ASMOS realizes comprehensive performance optimization and effectively breaks through the performance limitations of traditional 4H-SiC MOSFETs.
- Metal-Oxide-Semiconductor Field-Effect Transistor /
- Body diode /
- Source-Connected Gate /
- Reverse freewheeling /
- Bipolar degradation

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图 1 三种不同双沟槽MOSFET的结构示意图

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图 2 N_CSL对器件BV、R_on,sp、FOM的影响

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图 3 N_P-body对器件BV、E_GOX,max、V_F的影响

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图 4 W_CH3对器件V_F和BV的影响

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图 5 T_SOX对器件V_F和E_SOX,max的影响

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图 6 不同T_SOX下源极氧化层电场强度分布曲线

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图 7 不同T_SOX下的反向电流密度曲线

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图 8 三种器件结构导通状态下的有源区电流密度分布图

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图 9 RC-ASMOS反向导通时不同V_DS的电子密度分布图

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图 10 RC-ASMOS反向导通状态图

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图 11 三种器件结构主要特性对比曲线

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图 12 三种器件结构击穿时的电场分布图

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图 13 栅电荷特性曲线

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图 14 电容特性曲线

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图 15 反向恢复特性曲线

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图 16 开关特性

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图 17 RC-ASMOS的工艺流程图

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表 1 三种器件结构的主要结构参数

参数	CON-DTMOS(半元胞)	LV-DTMOS	RC-ASMOS
T_N-drift (μm)	10.0	10.0	10.0
N_N-drift (cm^–3)	5.0×10¹⁵	5.0×10¹⁵	5.0×10¹⁵
T_CSL (μm)	2.0	2.0	2.0
N_CSL (cm^–3)	4.5×10¹⁶	4.5×10¹⁶	4.5×10¹⁶
N_P⁺ (cm^–3)	1.0×10¹⁹	1.0×10¹⁹	1.0×10¹⁹
N_N⁺ (cm^–3)	1.0×10¹⁹	1.0×10¹⁹	1.0×10¹⁹
N_P-body (cm^–3)	2.0×10¹⁷	2.0×10¹⁷	2.0×10¹⁷
T_GOX (μm)	0.05	0.05	0.05
T_SOX (μm)	/	/	0.012
T_P-shield2 (μm)	/	2.0	1.2
T_P-shield1 (μm)	3.0	3.0	3.0
W_P-shield (μm)	0.7	0.7	0.7
T_cont1 (μm)	2.5	2.5	2.5
T_cont2 (μm)	1.5	1.5	1.5
W_cont (μm)	0.3	0.3	0.3
W_S (μm)	/	/	0.4
W_CH3 (μm)	/	/	0.35
W_CH2 (μm)	/	0.3	0.3
W_CH1 (μm)	0.3	0.3	0.3
W_cell (μm)	3.5	3.5	3.5
W_G (μm)	0.45	0.8	0.6

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表 2 三种器件结构的主要特性对比

电学特性	CON-DTMOS	LV-DTMOS	RC-ASMOS
R_on,sp (mΩ·cm²)	2.13	1.46	1.51
V_F (V)	2.8	2.8	1.6
BV (V)	1226	1305	1673
Q_GD (nC/cm²)	148.1	72.2	68.3
FOM_RQ (mΩ·nC)	315.5	105.4	103.1
Q_RR (μC/cm²)	0.26	0.26	0.14
I_RRM (A)	147.2	140.8	75.9
T_ON (μs)	0.0154	0.0055	0.0045
T_OFF (μs)	0.020	0.0153	0.0143

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