跨尺度功能安全验证：面向汽车系统级芯片的专家引导图学习

卞延浩; 孙宇涛; 费思飏; 王志君

doi:10.11999/JEIT260719

跨尺度功能安全验证：面向汽车系统级芯片的专家引导图学习

doi: 10.11999/JEIT260719 cstr: 32379.14.JEIT260719

北京邮电大学集成电路学院北京 100876

详细信息

作者简介:
卞延浩：男，博士生，研究方向为图神经网络、电路功能安全

孙宇涛：男，博士生，研究方向为电路选择性加固、系统级SoCs

费思飏：男，博士生，研究方向为大语言模型、电路功能安全

王志君：女，教授，研究方向为面向领域应用的超大规模异构SoC芯片架构、芯片功能安全

通讯作者:
王志君　wangzhijun@bupt.edu.cn

中图分类号: TN4; TP183
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出版历程
- 收稿日期: 2026-06-01
- 修回日期: 2026-08-27
- 录用日期: 2026-09-15
- 网络出版日期: 2026-09-24

Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for System-on-Chips

School of Integrated Circuits, Beijing University of Posts and Telecommunications, Beijing 100876, China

摘要

摘要: 针对汽车系统级芯片功能安全验证中传统故障注入成本过高、现有学习方法跨尺度迁移能力不足的问题，该文提出一种原语级故障数据集与专家引导图学习框架。该框架基于40个标准库原语构建统一图表示数据集，融入结构、时序等多维特征与节点级关键性标签。模型采用图注意力网络，并结合传播导向、安全上下文、置信度校正与电路自适应四层专家规则校准预测结果，实现跨尺度故障关键性预测；同时构建“预测-解释-加固”闭环，支持低开销选择性加固。在9个基准电路上的实验表明，该方法最高预测准确率达99.4%，较传统故障仿真最高加速1119倍；与全局三重模块冗余相比，面积开销降低8.35%～14.95%，8个电路达到ISO 26262 ASIL-D对应目标值。
- 电路功能安全性 /
- 汽车系统级芯片 /
- 故障注入 /
- 图神经网络 /
- 选择性加固
Abstract: Objective Functional safety has become a critical requirement in automotive System-on-Chip (SoC) design in compliance with the ISO 26262 functional safety standard. Conventional exhaustive fault injection faces prohibitive computational costs in large-scale circuits, which may result in insufficient identification of critical fault regions or overly conservative protection strategies. Existing learning-based methods still suffer from limited cross-scale transferability, insufficient integration of circuit-domain knowledge, and inadequate support for downstream hardening decisions. This work aims to develop an accurate, efficient, and transferable framework for node-level fault-criticality prediction and low-overhead selective hardening to support automotive SoC functional safety verification. Methods A primitive-level fault dataset is constructed from 40 DesignWare (DW) library circuits covering four functional families: arithmetic and logic, communication and encoding, storage and control, and error correction and detection. Each circuit is converted into a unified directed graph with structural, connectivity, timing, and activity-related features. Node-level fault-criticality labels are generated through controlled stuck-at fault injection with ASIL-aware threshold calibration. An expert-guided graph learning model is proposed, which adopts a Graph Attention Network (GAT) with residual connections to learn transferable fault-sensitive representations. A four-layer expert rule calibration module is further developed to incorporate circuit-domain knowledge. The propagation-oriented rules emphasize nodes with strong fault propagation capability, such as high fan-out and critical-path nodes; the safety-context rules enhance the evaluation of clock-domain crossings and reset-related logic; the confidence-correction rules reduce unstable predictions and false positives; and the circuit-adaptive rules dynamically adjust rule intensity according to different functional families. Furthermore, an explanation-based node ranking mechanism combining structural and feature attribution analyses is established to form a prediction-explanation-hardening closed-loop framework for targeted protection (Fig. 1, Fig. 2). Results and Discussions The proposed method is evaluated on nine benchmark circuits with gate counts ranging from 273 to 15 290. The results show that the method achieves an accuracy of up to 99.4% and outperforms GAT, CNN, and three state-of-the-art methods on all test circuits (Fig. 3, Table 4). The introduction of expert rules increases the average accuracy and F1 score by 1.77 and 1.98 percentage points, respectively, with greater improvements observed in complex circuits (Fig. 7, Fig. 8). Ablation experiments demonstrate that the four functional families provide complementary fault knowledge and jointly enhance cross-scale generalization capability (Fig. 5, Fig. 6). Compared with traditional fault simulation, the proposed framework achieves a geometric mean speedup of 166.4× and a maximum speedup of 1 119× on I2C, while the explainability module introduces only approximately 20% additional computational overhead (Fig. 9). The selective hardening strategy reduces area overhead by 8.35%～14.95% compared with global Triple Modular Redundancy (TMR), while maintaining the Single-Point Fault Metric (SPFM) above 99.3% and the Latent Fault Metric (LFM) above 89.0%. All nine circuits achieve the SPFM target value associated with ASIL-D, eight circuits satisfy both SPFM and LFM target values associated with ASIL-D, and the remaining circuit satisfies the corresponding ASIL-C target values (Fig. 10, Fig. 11). Conclusions The proposed framework enables effective cross-scale fault-criticality prediction by learning transferable fault-sensitive patterns from primitive circuits without retraining on target designs. It achieves high prediction accuracy, substantial acceleration, and low hardware overhead while satisfying ISO 26262-related functional safety requirements. Future work will expand primitive dataset coverage, incorporate causal inference to reduce dependence on manually designed expert rules, and explore extensions toward heterogeneous chiplet architectures.
- Functional safety /
- Automotive System-on-Chip (SoC) /
- Fault injection /
- Graph Neural Networks (GNN) /
- Selective hardening

HTML全文

图 1 跨尺度故障关键性分析整体框架图

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图 2 专家引导图学习方法整体架构

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图 3 不同方法在9个目标电路上的准确率与F1值对比

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图 4 单家族子集迁移平均准确率与F1值

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图 5 留一法消融实验性能热力图

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图 6 移除不同子集后的平均性能对比

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图 7 专家规则性能增益与电路复杂度相关性

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图 8 专家规则互补性分析

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图 9 本文方法与传统故障仿真的运行时间对比

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图 10 本文方法与全局TMR及已有方法的面积开销对比

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图 11 本文方法与全局TMR及已有方法的功能安全指标对比

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表 1 40个DW标准库原语电路信息

序号	功能家族	等效门数	核心功能说明	序号	功能家族	等效门数	核心功能说明
1	算术与逻辑	78	8位加法器	21	通信与编码	62	带使能的译码器
2		82	8位减法器	22		286	8b/10b编码器
3		112	8位加减法器	23		312	8b/10b解码器
4		95	8位数值比较器	24		184	串行CRC校验生成器
5		136	桶形移位器	25		372	并行CRC校验生成器
6		64	可配置多路选择器	26		45	4位边界扫描单元
7		328	16位并行乘法器	27		88	8位边界扫描单元
8		412	16位乘加(MAC)单元	28		256	用户定制JTAG TAP控制器
9		158	多输入累加求和单元	29		224	标准JTAG TAP控制器
10		482	单精度浮点加减法器	30		58	奇偶校验位生成器
11		396	16位整数除法器	31	存储与控制	386	同步FIFO控制器
12		72	绝对值计算单元	32		358	位宽异步FIFO控制器
13	纠错与检测	468	ECC纠错编解码器	33		128	轮询仲裁器
14		128	影子校验寄存器组	34		164	双优先级仲裁器
15		392	逆平方根运算单元	35		88	加减计数器
16		356	整数平方根运算单元	36		142	线性反馈移位计数器
17		324	带饱和处理的除法器	37		96	单时钟域数据同步器
18		288	单精度浮点比较器	38		72	异步复位同步器
19		426	低功耗流水线ECC单元	39		112	流水线寄存器组
20		72	可观测性数据生成器	40		156	堆栈控制器

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表 2 4层电路领域专家规则说明

规则图层	物理意义与作用	计算方式
传播导向$ {\varGamma }_{v}^{\text{prop}} $	强调故障传播能力强的区域	(1)关键路径强度>0.4时×1.15，0.2～0.4时×1.08； (2)扇出数>4时×1.12，2～4时×1.05； (3)I/O接口×1.06；
安全上下文$ {\varGamma }_{v}^{{\mathrm{safe}}} $	突出安全敏感的操作条件	(4)时序裕量<0.2时×1.10； (5)复位关联度>0.5时×1.09； (6)跨时钟域节点×1.08； (7)多电源域节点×1.07；
置信度校正$ {\varGamma }_{v}^{{\mathrm{corr}}} $	抑制不稳定预测与假阳性结果	(8)冗余等价节点×0.9； (9)扇入数>3时×1.05； (10)原始预测概率<0.1时×0.85；
电路自适应$ {\varGamma }_{v}^{{\mathrm{adapt}}} $	根据目标电路所属功能家族调整规则强度	存储与控制×1.04；算术与逻辑×1.03；通信与编码×1.02；纠错与检测×1.0；

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表 3 电路级故障关键性验证目标电路

电路名称	核心功能	门计数	与原语平均规模比
32位乘法器	整数乘法	4629	22.1×
32位MAC	乘法-累加单元	9621	46.0×
FFT	快速傅里叶变换模块	14221	68.0×
RISC-V CPU	嵌入式处理器核心	11445	54.8×
微型RISC	紧凑型处理器核心	15290	73.1×
I2C	串行通信控制器	273	1.3×
UART	异步串行通信	859	4.1×
FIFO	数据缓冲和有序传输	567	2.7×
CRC	CRC生成与验证	476	2.3×

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表 4 本文方法与领域 SOTA方法的性能对比(%)

电路	方法	准确率	F1值
UART	本文方法	99.20	99.79
	ICCAD 2025	97.55	98.62
	TCAS-I 2024	97.87	98.93
	DAC 2024	96.21	97.35
32 bit MUL	本文方法	98.14	98.80
	ICCAD 2025	95.85	97.12
	TCAS-I 2024	96.14	97.82
	DAC 2024	90.37	92.46
Tiny RISC	本文方法	97.01	97.90
	ICCAD 2025	92.55	94.22
	TCAS-I 2024	90.71	94.52
	DAC 2024	93.79	90.15

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表 5 专家规则性能提升的统计显著性与参数鲁棒性分析

(a)统计显著性检验
指标	提升量/百分点		95%置信区间		Wilcoxon p值
Accuracy	+1.77		[1.55, 1.98]		0.0039
F1	+1.98		[1.74, 2.20]		0.0039
(b)参数敏感性分析
扰动水平	平均Accuracy(%)	平均F1(%)	平均SPFM(%)	平均LFM(%)	达到ASIL-D指标目标值的电路数
标称系数	98.10	98.72	99.38	90.45	8/9
±5%扰动	98.08	98.70	99.37	90.42	8/9
±10%扰动	98.04	98.66	99.36	90.33	8/9

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