嵌入式FPGA架构参数化描述框架及多目标QoR架构探索

周婧; 张盛兵; 陈雷; 冯涵旭; 王硕; 田春生

doi:10.11999/JEIT260609

嵌入式FPGA架构参数化描述框架及多目标QoR架构探索

doi: 10.11999/JEIT260609 cstr: 32379.14.JEIT260609

周婧^{1, 2, ,},
张盛兵¹,
陈雷²,
冯涵旭²,
王硕²,
田春生²

1.
西北工业大学西安 710072
2.
北京微电子技术研究所北京 100070

详细信息

作者简介:
周婧：女，高工，研究方向为FPGA以及嵌入式FPGA架构设计、FPGA EDA软件设计

张盛兵：男，教授，研究方向为高性能计算体系结构、领域专用计算体系结构、集成电路设计

陈雷：男，研究员，研究方向为人工智能算法、集成电路设计

冯涵旭：男，工程师，研究方向为辐射效应、高可靠FPGA设计及应用

王硕：男，研究员，研究方向为FPGA EDA软件设计、FPGA EDA算法

田春生：男，高工，研究方向为FPGA EDA算法、高效布局布线算法

通讯作者:
周婧　zhoujing0915@mail.nwpu.edu.cn

中图分类号: TN47
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出版历程
- 收稿日期: 2026-05-14
- 修回日期: 2026-07-28
- 录用日期: 2026-07-29
- 网络出版日期: 2026-08-08

A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

1.
Northwestern Polytechnical University, Xi’an 710072, China
2.
Beijing Microelectronics Technology Institution, Beijing 100070, China

摘要

摘要: 相较于传统的货架FPGA，嵌入式FPGA的最大区别在于允许开发者根据特定应用的需求独立选择最合适的硬件架构参数(K, N、互连拓扑等)，这就使得架构空间探索不再仅仅是纯学术领域的研究方法，也是必须评估数十上百份架构文件并反复迭代选型的实际工程任务。现有的架构描述框架仍以手工编写架构文件与批处理脚本为主，每次参数调整都要在多份后端文件间逐处同步，难以支撑规模化的架构探索。针对此问题该文提出一种支持多后端架构文件统一描述的参数化架构描述框架，该框架将架构参数按独立性分为工艺常量、耦合参数与独立参数3层，各后端描述由独立的渲染函数自动派生。目前该框架已适配VPR, OpenFPGA, Yosys 3路后端并成功扩展至COFFE，并已通过跨工具链全流程验证。依托该框架批量生成架构描述文件，提出基于参数扫描的架构探索方法，系统扫描了查找表(LUT)输入数K与簇规模N的取值组合，从面积、关键路径延迟及二者乘积3个维度衡量每种参数配置的质量结果。结果显示，面积与延迟在(K,N)参数的优化偏好上呈相反方向。还公开发布了一份涵盖5个应用域、包含同构与异构架构的Quality of Results(QoR)数据集，可作为eFPGA架构空间探索的公共标准测试集。
- 嵌入式FPGA /
- 架构空间探索 /
- 参数化架构描述框架 /
- QoR数据集
Abstract: Objective Architecture parameters of commercial off-the-shelf Field-Programmable Gate Arrays (FPGAs) are fixed by vendors and reused across products. Embedded FPGAs (eFPGAs), in contrast, allow architects to select architecture parameters according to specific application requirements. The LUT input count K, the number of LUTs per cluster N, the interconnect topology, and the types of heterogeneous tiles can therefore be configured for the target application. Architecture design space exploration thus becomes an engineering task in which tens to hundreds of architectures may need to be generated and evaluated before a suitable configuration is selected. Existing architecture description practices rely largely on manually written architecture files and batch scripts. After each parameter change, shared fields across multiple backend toolchains must be updated and aligned manually, making large-scale architecture exploration difficult to support. To address this problem, a parametric architecture description framework is proposed for unified description across multiple backend toolchains. Architecture parameters are organized into three layers according to their independence: process invariants, coupled parameters, and independent parameters. Architecture descriptions for different backends are automatically derived from the same source object through independent derivation functions. The framework currently supports VPR, OpenFPGA, and Yosys and has been extended to COFFE. Its operation is validated across the complete toolchain. Based on the framework, a parameter-sweep design space exploration method is developed, and an open Quality of Results (QoR) dataset covering five application domains and 64 benchmark circuits, including homogeneous and heterogeneous architectures, is released as a public benchmark. Methods HorizonArch, the proposed parametric architecture description framework, organizes architecture parameters into three layers according to parameter independence (Table 1). L0 contains process invariants that are fixed once the technology node is determined. L1 contains coupled parameters, including K, N, tier, segment length, switch block type, and channel connectivity, for which a single parameter change can trigger updates across multiple fields and backend architecture descriptions. L2 contains independent parameters that can be specified separately. Architecture construction is formalized by an operator B that maps a parameter vector p to a complete architecture object (Fig. 4). Five formal rules are imposed: parameter completeness (R1), fragment independence (R2), type compatibility (R3), explicit coupling (R4), and static checkability (R5). Each backend architecture description is then derived by an independent derivation function from the same source object. Thus, adding a new backend requires only an additional view rather than modifications throughout the existing description structure. Field-level validation and cross-field validation are performed when the architecture object is loaded, before any backend tool is invoked. The class structure (Fig. 3) divides the architecture description into synthesis, circuit, and layout views, with each semantic element declared only once. Three extension levels are defined: G1 adds a black-box model, G2 extends the value set of an existing coupled parameter, and G3 adds a new coupled parameter together with its constrained value set. Based on this framework, a parameter-sweep design space exploration method is developed to scan the (K, N) parameter grid and heterogeneous tile configurations. Each configuration is evaluated using three QoR metrics: area, Critical-Path Delay (CPD), and Area-Delay Product (ADP). Results and Discussions End-to-end validation shows that a single source description consistently generates architecture descriptions for VPR, OpenFPGA, and Yosys. COFFE is connected and verified at the interface layer, including SPICE simulation startup (Table 4, Table 5). The G1, G2, and G3 extension experiments pass all cross-field checks. The design space exploration results show different preferences among area, CPD, and ADP across the (K, N) parameter space (Figs. 5 and 6). Area favors smaller K values, with K=4 and N=4 providing favorable area and ADP performance for a large proportion of circuits. CPD, in contrast, favors larger K and N values, with optimal configurations concentrated near (K, N)=(8, 10) and (7, 10). Across the twenty (K, N) configurations, the relative-range distribution shows that parameter selection has a much greater effect on area and ADP than on CPD (Table 6). The mean relative ranges are 50.9% for CPD, 675.1% for area, and 516.3% for ADP. A comparison of default configurations (Table 7) shows that K=4 and N=4 achieves the minimum ADP for 67.9% of the circuits and has an average ADP deviation of 5.8%, although its average CPD deviation reaches 47.9%. In contrast, K=8 and N=10 reduces the average CPD deviation to 5.9%, with 30.8% of the circuits achieving the CPD optimum, but increases the average area and ADP deviations to 673.2% and 487.0%, respectively. A random-forest cross-domain surrogate achieves a top-5 accuracy of approximately 65%. Therefore, parameter sweeping remains necessary when strict design targets are imposed. Conclusions HorizonArch, a parametric architecture description framework for eFPGA exploration, is developed and validated. The framework generates VPR, OpenFPGA, and Yosys backend architecture descriptions from a single source object and provides an extensible interface for COFFE. The parameter-sweep exploration shows that area and CPD favor opposite regions of the (K, N) parameter space. Therefore, eFPGA architecture parameters should be selected according to explicit design targets rather than fixed default values. An open QoR dataset covering five application domains and 64 benchmark circuits is also released as a reusable benchmark for eFPGA architecture design space exploration. Future work will complete the COFFE SPICE topology-rewriting component, refit the routing-area coefficient using measured data, and explore more efficient design space exploration strategies.
- Embedded FPGA (eFPGA) /
- Architecture Design Space Exploration (DSE) /
- Parametric architecture description framework /
- Quality of Results (QoR) dataset

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图 1 HorizonArch框架在FPGA架构描述工具谱中的定位

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图 2 L1耦合参数联动传播路径

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图 3 主要类结构及组合关系

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图 4 构造算子B的构造律

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图 5 按应用域和设计规模的每个最优(K,N)取值电路汇总

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图 6 3个指标在(K, N)网格上的强度热图

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表 1 字段层次化模型

层级	判定标准	典型例子	修改入口
L0工艺不变量	工艺节点决定即固定	r_minw、CLB/DSP绝对面积系数、金属层R/C	工艺预设
L1耦合参数	单一参数变动引发跨字段联动	K, N, tier, segment段长、$ {F}_{{\mathrm{s}}} $、switch_block类型、$ {F}_{{\mathrm{c}}} $	构造算子B
L2独立参数	可独立取值	features 列表项、架构名	架构实例直接声明

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表 2 架构描述框架的参数扩展能力

粒度	改动面	修改示例
G1YAML加条目	追加BlackboxModel与params.*_modes模式条目	双端口BRAM异构模块
G2现有参数加取值	数值参数追加取值，必要时扩展模板分支	BRAM容量、DSP位宽
G3加受约束枚举	新增枚举白名单及对应模板分支	进位链三种实现形式

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表 3 3类架构编写方法的能力对比

维度	手工	简单替换脚本	本框架
跨后端字段一致	人工对齐	在脚本内手写对齐逻辑	单源声明，变换同步
跨字段约束R1～R5	人工保证	不检查	加载期校验
新片段类型支持	重写架构	改脚本本身	G1～G3的扩展层级

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表 4 本文框架与已有开源架构工具的技术差异

维度	HorizonArch框架	OpenFPGA^[1]	iFAR^[16]	FABulous^[2]	PRGA^[3]
主要产出	HorizonArch+QoR数据集	可综合fabric	架构库+面积时序估计	tile级fabric	可组合fabric
工具链支持	3路核心工具链+COFFE扩展	2路	1路	1路	1路
架构描述格式	YAML+pydantic schema	扩展XML	XML手工编辑	CSV+模板	Python DSL
架构生成机制	构造算子B+规则校验	XML模板继承	手工模板替换	tile 级模板组装	Python类继承
扩展方式	G1～G3 3档扩展	沿用XML模板继承	XML手工修改	改模板	改Python类

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表 5 基于HorizonArch框架的eFPGA DSE方法

项	取值
应用域	crypto, comm, ctrl, dsp, ml
基准电路	64
K	4, 5, 6, 7, 8
N	4, 6, 8, 10
异构tile组合	LUT only, DSP, BRAM, DSP and BRAM both
每案例扫描配置	5 × 4 = 20 个 (K, N)对
案例总数	156
VPR 配置	VTR 8.0, $ L=4 $, $ \text{fc}\_\text{in=}0.15 $

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表 6 3种QoR的rel_range分布(%)

指标	均值	中位数	P90	rel_range>100%占比
CPD	50.9	48.5	75.7	3.8
area	675.1	740.1	935.6	98.1
ADP	516.3	509.4	742.0	97.4

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表 7 默认配置策略的多指标对比(%)

默认配置	CPD 平均偏离	area 平均偏离	ADP 平均偏离	对应 metric 命中率
随机选取	19.7	234.4	174.8	-
K=4, N=4	47.9	0.6	5.8	ADP 67.9
K=8, N=10	5.9	673.2	487.0	CPD 30.8

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