多负载网络最大跳变时间违例的ECO修复方法

樊凌雁; 许欣晨; 黄灿坤; 沈郑诺; 邓江峡; 刘海銮

doi:10.11999/JEIT260600

多负载网络最大跳变时间违例的ECO修复方法

doi: 10.11999/JEIT260600 cstr: 32379.14.JEIT260600

1.
杭州电子科技大学微电子研究院杭州 310018
2.
杭州华澜微电子股份有限公司杭州 311210

基金项目: 国家自然科学基金(U22A2071)

详细信息

作者简介:
樊凌雁：女，研究员，研究方向为数据存储，高速接口集成电路设计，邮箱　fanlingyan@hdu.edu.cn

许欣晨：男，硕士生，研究方向为数字集成电路物理设计

黄灿坤：男，博士生，研究方向为数字集成电路物理设计

沈郑诺：男，硕士生，研究方向为数字集成电路物理设计

邓江峡：女，副教授，研究方向为集成电路设计和仿真验证，邮箱　dengjiangxia@hdu.edu.cn

刘海銮：男，正高级高工，研究方向为数据存储，高速接口集成电路设计

通讯作者:
邓江峡　dengjiangxia@hdu.edu.cn

中图分类号: TN4;TN431.2
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出版历程
- 收稿日期: 2026-05-14
- 修回日期: 2026-08-13
- 录用日期: 2026-08-13
- 网络出版日期: 2026-08-25

An ECO Repair Method for Max Transition Violations in Multi-Load Nets

1.
Microelectronics Research Institute, Hangzhou Dianzi University, Hangzhou 310018, China
2.
Hangzhou Hualan Microelectronique Co., Ltd. Hangzhou 311210, China

Funds: The National Natural Science Foundation of China(U22A2071)

摘要

摘要: 在数字集成电路物理设计中，跳变时间是表征数字电路信号边沿过渡快慢的重要电气特性参数，最大跳变时间违例会导致门延迟增大、时序裕量下降，并可能带来额外功耗和信号完整性风险。传统修复方法通常依赖工程师对目标违例路径进行手工分析与处理，效率较低，且在多负载网络场景下容易出现修复不准确和冗余插入等问题。该文提出一种面向多负载违例路径的缓冲器插入优化方法，首先根据目标网络的物理路由信息恢复其物理拓扑结构，并利用向量投影法将违例端点映射到物理拓扑图中，再结合Dijkstra最短路径搜索恢复驱动端到目标违例负载端之间的实际物理路径。基于Elmore模型，将路径中点设为初始插入候选点，并构建缓冲器有效插入候选区间；针对多条违例路径共享公共物理段的情况，进一步提出基于候选区间交集的共享缓冲器优化策略，以减少冗余缓冲器插入数量。基于UMC 28 nm下5个设计的测试结果表明，该文方法对最大跳变时间违例的整体修复率达到98.98%，多负载违例路径修复率达到99.39%，且对整体时序扰动小，为复杂数字集成电路设计后期多负载网络最大跳变时间违例的ECO修复提供了具有实用性的思路。
- 最大跳变时间违例 /
- ECO修复 /
- 共享缓冲器优化
Abstract: Objective Max transition violations in digital integrated circuit physical design may increase gate delay, reduce timing margin, and introduce additional power-consumption and signal-integrity risks. With technology scaling and the increasing complexity of high-performance SoC and CPU designs, long interconnects and heavy effective loads make such violations more prominent in post-routing optimization and ECO stages. Conventional repair methods usually rely on manual analysis or global heuristics, such as total-wire-length-ratio-based buffer insertion, which may lead to low repair efficiency, inaccurate repair targeting, and redundant buffer insertion in multi-load nets. Although these approaches can alleviate some violations in simple cases, they often fail to accurately identify the real violating branches in multi-load nets. As a result, repair targeting becomes insufficient and redundant buffer insertion is likely to occur. To address these limitations, a path-level buffer insertion method is proposed for max transition violation repair in multi-load nets. Methods The proposed method first reconstructs the physical topology of the target net from routing information extracted from the Design Exchange Format (DEF) file. Routing endpoints, turning points, and via connection points are abstracted as physical nodes with coordinate and metal-layer attributes, and a weighted undirected graph is established to preserve branch structures and cross-layer connectivity (Fig. 3). To reduce the influence of small coordinate deviations, a spatial-tolerance-based node merging strategy is introduced during graph construction. Since the violation coordinates reported by timing analysis tools may not lie exactly on valid routed segments, a vector-projection-based coordinate snapping strategy is then adopted to align logical violation coordinates with the actual physical topology (Fig. 4). After endpoint binding, the actual physical propagation path from the driver to each violating load is recovered by Dijkstra shortest-path search. Based on the Elmore-model intuition that inserting a buffer near the midpoint of a long interconnect can effectively segment the distributed RC load, the midpoint of each recovered path is selected as the initial candidate insertion point. The exact insertion coordinate is obtained by accumulating segment lengths along the path and interpolating on the segment where half of the total path length is reached. To improve robustness, the initial candidate point is further expanded into an effective candidate interval with a spatial tolerance factor. For multi-load nets, different violating branches may share long common physical segments. Therefore, an interval-intersection-based shared-buffer optimization strategy is introduced to merge overlapping candidate intervals into shared insertion regions, thereby reducing redundant buffer insertion (Fig. 5-Fig. 7). Results and Discussions Experiments are conducted on five designs, including CPU, SAS, RAID, PCIe, and HBA, implemented in the UMC 28 nm process. Synopsys IC Compiler II is used for physical implementation, and PrimeTime is used for timing analysis. A violation-margin threshold of -8 ps is adopted, and only paths below this threshold are included in the repair and evaluation. The complete ECO flow retains the existing repair method for single-load nets and applies the proposed path-level method to multi-load nets. To illustrate the repair mechanism, a representative multi-load violating net is selected for detailed analysis. The net contains one driver and fourteen loads, among which thirteen violating load paths share a long common routed trunk and exhibit max transition violation margins ranging from -75.2 ps to -38.3 ps. If these paths are repaired independently, thirteen nearby buffer insertion demands are generated on the shared trunk. After interval-intersection-based merging, one shared buffer is sufficient to repair all thirteen violating paths jointly (Fig. 8). This case study indicates that path recovery improves repair targeting, while shared-buffer optimization improves resource efficiency. Across the five designs, the complete ECO flow reduces the total number of max transition violations from 10,616 to 108, corresponding to an overall repair rate of 98.98% (Table 1). The CPU, SAS, and RAID designs are completely repaired, while only 17 and 91 violations remain in PCIe and HBA, respectively. Among the 8,216 multi-load violating paths, 8,166 are successfully repaired, corresponding to a multi-load violation repair rate of 99.39%. If these successfully repaired paths were handled independently, 8,166 buffer insertions would be required. After shared-buffer optimization, only 1,548 buffers are inserted, giving an overall compression ratio of 81.04%. The setup worst negative slack, total negative slack, and number of violating paths remain generally stable before and after repair, with only minor fluctuations observed in individual designs (Table 2). These results show that the repair flow does not cause obvious degradation in setup timing quality. Further analysis indicates that the residual violations in PCIe and HBA mainly occur when candidate buffer locations fall inside standard-cell placement blockages around hard macros or IP cores. Metal routing is allowed through these regions, but buffers cannot be legally placed, revealing a current limitation in the physical-feasibility handling of candidate insertion locations. Conclusions A path-level buffer insertion method is proposed for max transition violation repair in multi-load nets. By combining physical topology reconstruction, violation-coordinate snapping, shortest-path-based path recovery, midpoint-guided candidate generation, and interval-intersection-based shared-buffer optimization, the proposed method improves repair targeting and reduces redundant buffer insertion. Experimental results on five designs show that the complete ECO flow reduces the number of max transition violations from 10,616 to 108, achieving an overall repair rate of 98.98%. Among the 8,216 multi-load violating paths, 8,166 are successfully repaired, corresponding to a repair rate of 99.39%. For these successfully repaired paths, shared-buffer optimization reduces the number of buffer insertion demands from 8,166 to 1,548, corresponding to a compression ratio of 81.04%, without causing obvious degradation in setup timing quality. The remaining violations are mainly associated with standard-cell placement blockages around hard macros or IP cores, indicating that the physical-feasibility handling of candidate insertion locations should be further improved.
- max transition violation /
- ECO repair /
- shared buffer optimization

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图 1 信号跳变时间示意图

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图 2 传统比例插入策略局限性示意图

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图 3 物理版图与拓扑图模型的映射关系示意图

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图 4 基于向量投影的违例坐标吸附示意图

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图 5 共享缓冲器候选区间合并流程图

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图 6 多负载网络中共享缓冲器合并机制

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图 7 缓冲器插入候选区间合并机制

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图 8 典型多负载网络共享缓冲器插入结果示意图

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1 基于Dijkstra的最短路径算法

1 Initialize dist[n] ← ∞ for all nodes, dist[d] ← 0
2 Initialize prev[n] ← null, PriorityQueue ← {(0, d)}
3 While PriorityQueue is not empty:
4 　(nd, u) ← PopMin(PriorityQueue)
5 　If u == $ {l}_{i} $: break
6 　For each neighbor v of u with edge weight w:
7 　　If nd + w < dist[v]:
8 　　　dist[v] ← nd + w, prev[v] ← u
9 　　　Push(PriorityQueue, (dist[v], v))
10 $ {P}_{i} $ ← Backtrack(prev, d, $ {l}_{i} $)
11 $ {L}_{i} $ ←dist[$ {l}_{i} $]
12 Return ($ {P}_{i},{L}_{i} $)

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表 1 不同设计的违例修复与共享缓冲器优化结果

设计	修复前违例数量(条)			修复后违例数量(条)			共享优化后缓冲器数量(个)	多负载网络
设计	总违例数	单负载违例	多负载违例	总违例数	单负载违例	多负载违例	共享优化后缓冲器数量(个)	缓冲器压缩率(%)
CPU	178	71	107	0	0	0	61	42.99%
SAS	180	62	118	0	0	0	21	82.20%
RAID	580	48	532	0	0	0	132	75.19%
PCIe	2509	512	1997	17	9	8	409	79.44%
HBA	7169	1707	5462	91	49	42	925	82.93%
注：逐路径独立修复时，每条成功修复的多负载违例路径对应1个缓冲器插入需求；共享优化后缓冲器数为采用候选区间合并机制后实际插入的缓冲器数量。缓冲器压缩率按照修复掉的多负载违例路径数与共享优化后缓冲器数计算。

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表 2 不同设计修复前后的建立时间质量对比

设计	Setup WNS(ns)		Setup TNS(ns)		Setup NVP(条)
设计	修复前	修复后	修复前	修复后	修复前	修复后
CPU	–0.499	–0.504	–245.900	–245.100	1783	1772
PCIe	–0.518	–0.428	–51.700	–52.200	590	616
HBA	–0.580	–0.580	–324.300	–287.100	2279	2017
SAS	0.000	0.000	0.000	0.000	0	0
RAID	–0.119	–0.114	–0.500	–0.400	13	11

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