基于国产化NPU的LDPC设计

汪天生; 韩凯峰; 陈力; 杜滢

doi:10.11999/JEIT260172

基于国产化NPU的LDPC设计

doi: 10.11999/JEIT260172 cstr: 32379.14.JEIT260172

汪天生^1,,
韩凯峰^2, ,,
陈力^1,,
杜滢^2,

1.
中国科学技术大学电子工程与信息科学系合肥 230026
2.
中国信息通信研究院无线与移动通信研究所北京 100191

详细信息

作者简介:
汪天生：男，硕士生，研究方向为移动通信与智能计算的融合

韩凯峰：男，高级工程师，研究方向为6G通感智算一体化技术研究

陈力：男，特任教授，研究方向为下一代无线网络中通信、感知和计算的融合

杜滢：女，正高级工程师，研究方向为5G-A/6G标准化和产业化研究

通讯作者:
韩凯峰　hankaifeng@caict.ac.cn

中图分类号: TN911.22
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出版历程
- 修回日期: 2026-10-28
- 录用日期: 2026-10-28
- 网络出版日期: 2026-10-31

Design of LDPC Based on Domestic NPU

WANG Tiansheng^1
,,
HAN Kaifeng^{2
, ,},
CHEN Li^1
,,
DU Ying^2
,

1.
Department of Electronic Engineering and Information Science, University of Science and Technology of China, Hefei 230026, China
2.
China Academy of Information and Communications Technology, Institute of Wireless and Mobile Communications, Beijing 100191, China

摘要

摘要: 6G是新一代智能化综合性数字信息基础设施，将一体化实现通信、感知、计算、智能等功能。基站作为6G无线接入网侧的核心产品形态，正在逐步演变为集通信、计算与AI服务于一体的边缘智能信息服务节点，国产NPU等AI算力芯片正在逐步引入基站侧。利用国产NPU算力实现通信物理层与AI服务的同平台部署，是提升基站算力资源利用率的重要路径。然而，作为物理层关键技术之一的LDPC算法的传统实现通常依赖不规则消息索引访问，其数据组织方式与NPU面向规则张量计算的数据流执行模式存在一定差异，难以直接高效部署。针对上述问题，本文面向昇腾Ascend处理器的达芬奇架构，提出了一种全张量化的并行LDPC译码框架DaVinci-LDPC。首先，针对稀疏矩阵的不规则性，构建了静态图拓扑映射机制，将因子图连接转化为固定的张量索引，大幅减少了运行时的动态分支开销；其次，针对稀疏图随机访存导致的显存带宽瓶颈，提出双重聚合消息传递策略，利用昇腾NPU的向量计算单元高效处理节点间的信息交互；最后，针对算法中双曲函数运算难以向量化以及NPU半精度计算易溢出的问题，设计了向量化双曲正切算子融合方案，在FP16半精度下实现了校验节点更新的高度并行。实验结果表明，DaVinci-LDPC方案在译码精度满足实际通信系统的规范下相较于CPU稀疏实现取得了14.09倍的峰值加速比。
- LDPC码 /
- 昇腾NPU /
- 达芬奇架构 /
- 并行计算
Abstract: Objective 6G represents a new generation of intelligent, comprehensive digital information infrastructure, integrating communication, sensing, computation, and intelligence. As the core component of the 6G wireless access network, the base station is evolving into an edge-intelligent service node that unifies communication and AI services. Consequently, domestic Artificial Intelligence (AI) accelerators, such as Neural Processing Units (NPUs), are being integrated into base station architectures. Deploying both communication physical layer tasks and AI services on a unified NPU-based platform is essential for maximizing hardware resource utilization. However, Low-Density Parity-Check (LDPC) algorithms, One of the key technologies of physical layer, exhibit non-contiguous memory access patterns due to their sparse graph structures. This creates a fundamental mismatch with the tensor-centric computational architecture of NPUs, hindering efficient deployment. To resolve this, this paper proposes DaVinci-LDPC, an all-tensorized parallel LDPC decoding framework designed specifically for the DaVinci architecture of Huawei Ascend NPUs. Methods To bridge the gap between irregular sparse graphs and rigid tensor hardware, this research implements three key optimization strategies. First, a static graph topology mapping mechanism is constructed to transform factor graph connections into fixed tensor indices, which eliminates dynamic branching during runtime and significantly reduces control-flow overhead. Second, to overcome the memory bandwidth bottlenecks caused by random access, a dual-gather message passing strategy is proposed to efficiently manage information interaction between nodes by utilizing the NPU’s vector calculation units. Finally, a vectorized hyperbolic tangent operator fusion scheme is designed to address the challenges of non-linear function vectorization and potential numerical overflow in FP16 half-precision calculations, enabling highly parallel check node updates while maintaining numerical stability. Results and Discussions The performance of the DaVinci-LDPC framework was evaluated against a highly optimized CPU baseline and strict communication standards. Experimental results demonstrate that while 5G/6G data channels typically require a Bit Error Rate (BER) in the 10^–5 range, the NPU-based FP16 implementation maintains a BER in the 10^–7 range (Fig. 4), confirming that the precision loss from half-precision computation is well within practical specifications. In terms of throughput, the NPU implementation demonstrates superior scalability as code length increases (Table 2, Fig. 5), achieving a peak performance speedup of 14.09x compared to the optimized CPU baseline (Table 2). Conclusions This study designs and implements an efficient LDPC parallel decoding system on the domestic Huawei Ascend NPU platform, successfully validating the NPU’s acceleration capabilities for 5G/6G physical layer algorithms. By optimizing graph mapping, message passing, and core operators, the DaVinci-LDPC framework resolves the structural mismatch between sparse LDPC factor graphs and the DaVinci tensor architecture. The resulting system achieves high throughput and numerical stability while meeting strict communication accuracy requirements. This work provides a valuable reference for the future deployment of AI-native, software-defined 6G physical layer infrastructures using domestic AI hardware.
- LDPC codes /
- Ascend NPU /
- DaVinci Architecture /
- Parallel computing

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图 1 PC编译码系统模型

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图 2 向量单元的计算逻辑

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图 3 U实现LDPC模型框架

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图 4 误码率性能对比图

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图 5 U与NPU吞吐量对比

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表 1 实验环境和参数

	NPU	CPU
处理器	华为Ascend 910AI处理器	Intel Xeon Gold 6248CPU
软件栈	CANN8.1、PyTorch2.5.1	Python3.8、Numba JIT编译器
码字构造	码长N∈{512，1024，2048，4096}，码率固定为1/2	同NPU
信道环境	BPSK调制、AWGN信道、信噪比扫描范围0～3.5 dB	同NPU
批大小调优	Batch=8192	Batch=128

下载: 导出CSV

表 2 不同码长下的吞吐量对比

码长(N)	CPU吞吐量(Mbps)	NPU吞吐量(Mbps)	加速比(Speedup)
512	11.5	15.8	1.37x
1024	10.8	30.1	2.78x
2048	10.6	122.8	11.63x
4096	9.5	134.2	14.09x

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