A Survey of Processor Security
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摘要: 处理器芯片安全是信息安全的基石。长期以来，各种密码算法、应用程序和操作系统都以处理器作为可信基础。然而，随着摩尔定律的减缓，现代处理器在微架构设计中不断追求高性能和低功耗的目标，而忽视了安全性，导致近期安全漏洞频发。其中，以Meltdown和Spectre为代表的微架构时间信道漏洞备受关注，它们利用微架构状态变化引起的时间差异来突破基础的软硬件隔离，影响数十亿台主流CPU厂商的设备。此外，由于架构与微架构之间的界限变得模糊，催生了一系列新的攻击方式，使得时间信道从“硬件漏洞”发展为系统级安全问题。然而，现有文献主要基于硬件组件进行分类，掩盖了时序泄露的潜在共性，并限制了对软件信道分析的能力。该文对时间信道进行跨层综述，将基于硬件的和基于软件的泄漏统一在1个共同的抽象模型下。具体而言，该文首先分析了时间信道产生的4个基本条件，并根据核心泄露条件中共享可变状态的性质以及时间观测能力产生的机制将现有的软硬件攻击统一在1个分类模型下。基于该分类，该文全面回顾了近10年的攻击方法，系统地分析了它们的攻击步骤，并揭示了它们之间的共性。其次，基于阻断的泄露条件，对现有的防御技术进行分类，并指出防御的作用范围与失效原因。最后，总结了当前的自动化检测方法并对新兴平台下的时间信道安全研究与未来发展趋势进行了前瞻性的讨论。Abstract:
Significance Processor security is a cornerstone of modern information security. Cryptographic algorithms, operating systems, and applications have long relied on processors as trusted computing bases. However, as Moore’s Law slows, modern processors increasingly adopt aggressive microarchitectural optimization techniques to improve performance and energy efficiency, often without sufficient security consideration. This trend has led to frequent security vulnerabilities in recent years. In particular, microarchitectural timing channels, exemplified by Meltdown and Spectre, exploit timing differences caused by microarchitectural state changes to break fundamental hardware and software isolation, affecting billions of devices worldwide. At the same time, the boundary between architectural and microarchitectural behavior has become less clear, giving rise to new attack paradigms and turning timing channels from isolated hardware flaws into cross-layer system security problems. Progress Although substantial progress has been made in the study of timing channels, existing surveys still have several limitations. First, the mechanisms of timing channels are highly diverse, and the set of exploitable components continues to grow. Hardware-centric classification schemes are therefore insufficient to capture emerging and previously unknown attacks, and they often obscure the common features shared across different techniques. Second, as traditional microarchitectural channels become better understood and partially mitigated, leakage increasingly shifts to higher-level shared resources, including operating system policies and software-managed shared resources. However, previous studies have often treated software mainly as an execution context rather than a direct source of timing leakage. In addition, current discussions of defenses tend to emphasize individual techniques, with limited analysis of their scope and failure modes. Contributions This survey systematically reviews timing channels from a cross-layer perspective and unifies hardware- and software-based timing channels under a common abstraction. Four necessary conditions for timing channel exploitation are identified, and a unified classification framework is established based on the nature of shared mutable state and the mechanisms that make timing differences observable. Within this framework, representative attacks from the past decade are comprehensively reviewed, their attack procedures are systematically analyzed, and their common features are clarified. In addition, existing defense mechanisms are classified according to the leakage conditions they are intended to disrupt, and their scope and possible failure modes are examined. This survey also reviews current automated vulnerability detection methods. Prospects Future research on timing channels faces several emerging challenges. New microarchitectural optimization techniques continue to create new attack surfaces, while resource sharing at the software level may produce additional forms of timing leakage. Moreover, emerging platforms, including chiplet-based architectures, cloud computing environments, hardware accelerators, and heterogeneous systems, are likely to expose new types of timing channels that require systematic study. -
Key words:
- Processor security /
- Timing channels /
- Side-channel attacks /
- Transient execution
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表 1 跨层时间信道攻击的统一分类体系
泄露条件 攻击类别 硬件信道实例 软件信道实例 共享状态在
上下文切换
后仍然保留状态驻留类 微架构的持久状态 TLB[11], LLC[2,12], BTB[13] -† 架构的持久状态 DRAMA[14], LLM[15], MetaLeak[16] Page[5], Write+Sync[17], SLUB[6] 并发使用导致
带宽降低/
性能下降资源竞争类 结构性竞争 提交单元[18]、带宽[19]、Reload+Reload[20],
LeakyHammer[21]KernelSnitch[22], Sync+Sync[23] 仲裁型竞争 CPU环互连[24]、PCIe[25], Mesh[26] MES-Attacks[27,28] 状态实现被延迟，
快慢路径可区分延迟转换类 故障/中断触发延迟 SegScope[29], Thermalscope[30], Keydrown[31], WAIT[32] 写时复制[33] 惰性切换延迟 LazyFP[34] -† 基于历史行为的
预测或
自适应优化异步反馈类 预取类 GoFetch[35], PrefetchX[36] BunnyHop[37], Prefetchw[38] 预测执行类 Spectre-PHT[3], Spectre-RSB[39], RIDL[40],
Fallout[41], ARMeD[42]、循环预测机制[43]-† 异常/故障类 Meltdown[4], Foreshadow[44] -† 注：†表示当前未发现对应的实例。 
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表 2 时间信道防御技术分类
防御类别 防御范围/目标 典型实例 防御开销 基于隔离 分支预测器隔离 异步反馈类(分支预测攻击) BRB[47] 3.5%～5.5% XOR-BP [48] 约2.5%, 0.24%(硬件开销) HyBP[49] 0.5%, 21.1%(硬件开销) 缓存隔离 状态驻留类(缓存侧信道) PhantomCache[50] 0.5%～1.2% DAWG[51] <2% 敏感目标隔离 异步反馈类(异常/故障攻击) Site Isolation[52] 9%～13%(内存开销) KAISER[53] 1～10% 限制可观测的
微架构状态变化限制推测执行 异步反馈类(预测执行攻击) Retpoline[54] 5～10% CSF[55] <8% 添加硬件结构 异步反馈类(预测执行与
异常/故障攻击)InvisiSpec[56] 22%, 3.5%(面积开销) TreasureCache[57] <0.5%(硬件开销) CleanupSpec[58] 5.1%, 约1 kB(存储开销) 撤销或阻止不安全
推测的影响异步反馈类(预测执行与
异常/故障攻击)NDA[59] 10.7%～125% SCSGuardian[60] 3.82%～5.97% 时间侧信道 干扰隐蔽信道
的测量注入
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