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一种应用于GNSS接收机的新型低功耗高速预分频

于云丰 马成炎 叶甜春

于云丰, 马成炎, 叶甜春. 一种应用于GNSS接收机的新型低功耗高速预分频[J]. 电子与信息学报, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842
引用本文: 于云丰, 马成炎, 叶甜春. 一种应用于GNSS接收机的新型低功耗高速预分频[J]. 电子与信息学报, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842
Yu Yun-feng, Ma Cheng-yan, Ye Tian-chun. A New Low-Power High-Speed Prescaler in GNSS Receivers[J]. Journal of Electronics & Information Technology, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842
Citation: Yu Yun-feng, Ma Cheng-yan, Ye Tian-chun. A New Low-Power High-Speed Prescaler in GNSS Receivers[J]. Journal of Electronics & Information Technology, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842

一种应用于GNSS接收机的新型低功耗高速预分频

doi: 10.3724/SP.J.1146.2009.00842

A New Low-Power High-Speed Prescaler in GNSS Receivers

  • 摘要: 该文设计了一款应用于全球卫星导航系统(GNSS)接收机射频芯片的基于新型源耦合锁存器结构的预分频,用于产生接收机所需要的本振信号。与传统的静态源耦合逻辑锁存器相比,新结构引入一个钟控晶体管,可实现在采样期间减小锁存器的时间常数,有效地提高了最高工作频率,并且扩展了工作频率范围。通过建立一个简单但有效的小信号模型,新结构的优点被详细阐述。实验结果显示,该预分频最高频率可达6.9 GHz,消耗电流仅为1.2 mA。该预分频在0.18 m CMOS工艺上实现,已成功应用于GNSS接收机射频芯片中。
  • [1] Henzler S and Koeppe S. Design and application of power optimized high-speed CMOS frequency dividers[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2008, 16(11):1513-1520 [2] Kim D D, Cho Choong-yeun, and Kim Jong-hae. Scalable statistical measurement and estimation of a mmwave CML static divider sensitivity in 65nm SOI CMOS[C]. 2008 IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, Georgia, June 15-17, 2008: 625-628. [3] Park D M and Cho S H. A 18 V 900 W 4.5 GHz VCO and prescaler in 0.18 m CMOS using charge-recycling technique[J].. IEEE MicroWave and Wireless Components Letters.2009, 19(2):104-106 [4] Jang Sheng-Lyang, Lin Chi-Wen, and Liu Cheng-Chen, et al.. An active-inductor injection locked frequency divider with variable division ratio[J].IEEE MicroWave and Wireless Components Letters.2009, 19(1):39-41 [5] Mohanavelu R and Heydari P. A novel 40-GHz flip-flop-based frequency divider in 0.18m CMOS[C]. 31st European Solid-State Circuits Conference(ESSCIRC 2005), Grenoble, France, Sept. 12-16, 2005: 185-188. [6] Farazian M, Gudem P S, and Larson L E. A CMOS multi-phase injection-locked frequency divider for V-band operation[J].IEEE Microwave and Wireless Components Letters.2009, 19(4):239-241 [7] Mo Yuan, Skafidas E, and Evans R, et al.. Analysis and design of a 50-GHz 2:1 CMOS CML static frequency divider based on LC-tank[C]. European Microwave Integrated Circuit Conference, Amsterdam, Netherlands, Oct. 27-28, 2008: 64-67. [8] Razavi B, Lee K F, and Yan R H. A 13.4-GHz CMOS frequency divider[C]. IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, Feb. 16-18, 1994: 176-177. [9] Wang Hong-mo. A 1.8V 3mW 16.8GHz frequency divider in 0.25m CMOS[C]. IEEE International Solid-state circuits Conference, San Francisco, CA, USA, Feb.7-9, 2000: 196-197. [10] Wong M C, Cheung S L, Luong H C. A 1-V 25-mW 5.2-GHz frequency divider in a 0.35-m CMOS process[J].. IEEE Journal of Solid-State Circuits.2003, 38(10):1643-1648 [11] Shinmyo A, Hashimoto M, and Onodera H. Design and optimization of CMOS current mode logic dividers[C]. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC2004), Fukuoka, Japan, Aug. 4-5, 2004: 434-435. [12] Singh U and Green M. Dynamics of high-frequency CMOS dividers[C]. 2002 IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA, May 26-29, 2002: 421-424. [13] Lu Jian-hua, Wang Zhi-gong, and Tian Lei, et al.. An 8.5GHz 1:8 frequency divider in 0.35m CMOS technology[J]. Chinese Journal of Semiconductors, 2003, 24(4): 366-369.
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出版历程
  • 收稿日期:  2009-06-03
  • 修回日期:  2010-01-18
  • 刊出日期:  2010-07-19

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