一种基于匹配理论的FPGA三级互连网络测试方法

刘军华; 杨海钢; 李威

doi:10.3724/SP.J.1146.2008.00538

一种基于匹配理论的FPGA三级互连网络测试方法

doi: 10.3724/SP.J.1146.2008.00538

刘军华^{①②;杨海钢},
杨海钢,
李威

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- 被引次数: 0
出版历程
- 收稿日期: 2008-04-28
- 修回日期: 2008-12-16
- 刊出日期: 2009-06-19

A Novel Testing Method Based on Matching Theory for Three Stage Interconnect Network in FPGA

Liu Jun-hua^{①②;杨海钢},
Yang Hai-gang,
Li Wei

摘要

摘要: 针对FPGA中包含三级可编程开关的互连网络测试，该文提出了一种基于匹配理论的减少配置次数并且与阵列规模无关的测试方法。该方法通过建立结构测试图，按照图的道路长进行分块并应用最小覆盖和最大匹配的原理减少配置次数。对于不同的互连网络结构，与其它方法相比，该方法的配置次数至少减少了10%，并且与阵列规模无关。
- FPGA; 互连网络; 匹配理论; 测试配置次数
Abstract: Aimed to testing interconnect network that includes 3-stage programmable switches in FPGA, this paper proposes a novel size-independent approach based on a matching theory to minimize the number of test configurations. By constructing the graph of structure test, this paper presents a slicing scheme based on the path pace of the graph, and a method that applies the minimum coverage and maximum matching principle from the graph theory to obtain the minimum number of test configurations. For different interconnect network structure, the number of test configurations in the proposed method is reduced by at least 10% compared with other methods.

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Altera Corporation and Cyclone Architecture. CycloneFPGA Family Date Sheet, Ver1.5 Jan. 2007.[2]Yarandi M.[J].Alaghi A, and Navabi Z. An optimized BISTarchitecture for FPGA look-up table testing[C]. IEEEComputer Society Annual Symposium on Emerging VLSITechnologies and Architectures (ISVLSI06), Karlsruhe,Germany.2006,:-[3]Toutounchi S and Lai A. FPGA test and coverage[C].Proceedings IEEE International Test Conference, Baltimore,MD, USA, 2002: 599-608.[4]Lemieux G and Lewis D. Design of Interconnection Networksfor Programmable Logic[M]. Kluwer Academic Publishers,2004: 83-84.[5]Ahmed E and Rose J. The effect of LUT and cluster size ondeep-submicron FPGA performance and density[J].IEEETrans. on VLSI.2004, 12(3):288-298[6]Huang W K, Meyer F J, and Chen X T, et al.. Testingconfigurable LUT-based FPGA' s[J].IEEE Trans. on VeryLarge Scale Integration Systems.1998, 6(2):276-283[7]Renovell M, Portal J M, Figueras J, and Zorian Y. Testingthe configurable interconnect/logic interface of SRAM-basedFPGAs[C]. Proceedings of the Design, Automation and Testin Europe Conference and Exhibition, Munich, Germany,1999: 618-622.[8]Smith J, Xia T, and Stroud C. An automated BISTarchitecture for testing and diagnosing FPGA interconnectfaults[J].Journal of Electronic Testing: Theory andApplications.2006, 22(3):239-253[9]Sun X, Ogden K, Chan H, and Trouborst P. A novel FPGAlocal interconnect test scheme and automatic TCderivation/generation[J].Journal of Systems Architecture.2004, 50(5):267-280[10]Stroud C, Wijesuriya S, Hamilton C, and Abramovici M.Built-in self-test of FPGA interconnect[C]. Proceedings ofIEEE International Test Conference, Washington, DC, USA,1998: 404-410.[11]Synopsysy, DFT Compiler User Guide: Scan VersionZ-2007.03, June 2007.[12]王树禾. 图论及其算法[M]. 合肥: 中国科学技术大学出版社,1990: 246-253.[13]李建中, 骆吉洲. 图论导引[M]. 北京: 机械工业出版社, 2006:84-105.

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