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应用于数字DC-DC转换器的高分辨率数字脉宽调制器设计

张章 崔明辉 李斌 程心 解光军

张章, 崔明辉, 李斌, 程心, 解光军. 应用于数字DC-DC转换器的高分辨率数字脉宽调制器设计[J]. 电子与信息学报, 2020, 42(11): 2819-2826. doi: 10.11999/JEIT190482
引用本文: 张章, 崔明辉, 李斌, 程心, 解光军. 应用于数字DC-DC转换器的高分辨率数字脉宽调制器设计[J]. 电子与信息学报, 2020, 42(11): 2819-2826. doi: 10.11999/JEIT190482
Zhang ZHANG, Minghui CUI, Bin LI, Xin CHENG, Guangjun XIE. High Resolution Digital Pulse Width Modulation Design for Digital DC-DC Converter[J]. Journal of Electronics & Information Technology, 2020, 42(11): 2819-2826. doi: 10.11999/JEIT190482
Citation: Zhang ZHANG, Minghui CUI, Bin LI, Xin CHENG, Guangjun XIE. High Resolution Digital Pulse Width Modulation Design for Digital DC-DC Converter[J]. Journal of Electronics & Information Technology, 2020, 42(11): 2819-2826. doi: 10.11999/JEIT190482

应用于数字DC-DC转换器的高分辨率数字脉宽调制器设计

doi: 10.11999/JEIT190482
基金项目: 国家自然科学基金(61674049),中央高校基本科研业务费(PA2018GDQT0017, JZ2019HGTB0092),中国科学院苏州纳米技术与纳米仿生研究所纳米器件与应用重点实验室开放基金(18ZS03)
详细信息
    作者简介:

    张章:男,1982年生,副教授,硕士生导师,研究方向为集成电路设计与测试及新型半导体器件

    崔明辉:男,1995年生,硕士生,研究方向为集成电路设计

    李斌:男,1995年生,硕士生,研究方向为集成电路设计

    程心:女,1985年生,副教授,硕士生导师,研究方向为集成电路设计与测试及新型半导体器件

    解光军:男,1970年生,教授,博士生导师,研究方向为新型半导体器件及量子电路

    通讯作者:

    程心 ceciliacheng1013@163.com

  • 中图分类号: TN76

High Resolution Digital Pulse Width Modulation Design for Digital DC-DC Converter

Funds: The National Natural Science Foundation of China (61674049), The Fundamental Research Funds for Central Universities (PA2018GDQT0017, JZ2019HGTB0092), The Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS (18ZS03)
  • 摘要: 数字控制在电力电子领域的优势使得数字脉冲宽度调制的使用日益增加,然而其分辨率不足一直是制约开关电源领域中数字控制技术发展的主要因素之一。针对高分辨率数字脉冲宽度调制的应用需求,该文提出一种基于高速进位链结构的高分辨率数字脉冲宽度调制电路。该电路采用计数器、比较器、固定相移锁相环单元及高速进位链的混合结构,有效地提高了分辨率,并在Altera的Cyclone IV低成本现场可编程门阵列器件上实现。实验结果显示,当输入参考时钟工作频率为70 MHz时,该结构的分辨率可达到56 ps。此外,该电路还具有较宽的开关频率调节范围及较好的线性度等优点。
  • 图  1  数字控制开关电源的拓扑结构

    图  2  基于计数器和PLL的DPWM结构及其时序波形

    图  3  混合DPWM的高速进位链结构图

    图  4  进位链的关键路径

    图  5  基于高速进位链的混合DPWM电路结构

    图  6  基于高速进位链的混合DPWM电路时序分析

    图  7  相移时钟信号trg_delay在相移大于180°时的功能仿真波形

    图  8  输入数据流信号$\Delta $duty为16位变化时对应输出DPWM的验证波形

    图  9  输入数据流信号duty与正脉冲持续时间

    图  10  基于高速进位链混合结构的DPWM占空比调节范围

    表  1  输入数据流信号duty对应的输出理想延迟时间和输出占空比命令

    ${\bf{duty}}\left( {{{M}} - {\bf{1:0}}} \right)$$ {{t}}_{\bf{D}} $${{D} }_{{K} }{{D} }_{ { {{K} }{\rm{-} }1} }···{{D} }_{\bf{1} }{{D} }_{\bf{0} }$
    00···000010000···00
    00···001$ {t}_{\rm{c}} $$ 01000···00 $
    00···010$ 2{t}_{\rm{c}} $$ 00100···00 $
    $. $$. $$. $
    $. $$. $$. $
    $. $$. $$. $
    11···111$ K{t}_{\rm{c}} $$ 00000···01 $
    下载: 导出CSV

    表  2  基于FPGA器件不同结构时间分辨率结果对比

    设计结构输入时钟频率(MHz)开关频率(MHz)时间分辨率(ps)
    文献[8]LUT_based20025500
    文献[9]IODELAY_based2002578
    文献[10]Counter_DA_based6012.3
    文献[11]Delay-line_based/5200
    本文PLL & Carry Chain_based708.7556
    下载: 导出CSV
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出版历程
  • 收稿日期:  2019-06-28
  • 修回日期:  2020-03-29
  • 网络出版日期:  2020-08-27
  • 刊出日期:  2020-11-16

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