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一种新型低功耗抗软错误锁存器

张章 周宇澄 刘俊丞 程心 解光军

张章, 周宇澄, 刘俊丞, 程心, 解光军. 一种新型低功耗抗软错误锁存器[J]. 电子与信息学报, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191
引用本文: 张章, 周宇澄, 刘俊丞, 程心, 解光军. 一种新型低功耗抗软错误锁存器[J]. 电子与信息学报, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191
ZHANG Zhang, ZHOU Yucheng, LIU Juncheng, CHENG Xin, XIE Guangjun. A Novel Low Power Consumption Soft Error-tolerant Latch[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191
Citation: ZHANG Zhang, ZHOU Yucheng, LIU Juncheng, CHENG Xin, XIE Guangjun. A Novel Low Power Consumption Soft Error-tolerant Latch[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2520-2525. doi: 10.11999/JEIT170191

一种新型低功耗抗软错误锁存器

doi: 10.11999/JEIT170191
基金项目: 

国家自然科学基金(61404043, 61674049, 61401137)

A Novel Low Power Consumption Soft Error-tolerant Latch

Funds: 

The National Natural Science Foundation of China (61404043, 61674049, 61401137)

  • 摘要: 该文提出一种新型的C单元的连接方法,将距离输出节点比较远的P型和N型晶体管的栅端与C单元的输出节点相连接,利用晶体管自身的反馈机制形成反馈路径,实现了自恢复功能,因此大幅降低动态消耗和硬件开销;采用点加强型C单元作为输出级电路并进行优化,使得电路抵御单粒子翻转的能力更强;基于上述改进,搭建出一个新的抗软错误锁存器,将输入信号经过传输门以后接传到输出端,以降低输入信号传到输出节点的延迟,利用节点之间的反馈比较机制进一步提升各个电路节点的临界电荷量。在22 nm的先进工艺下进行仿真,实验结果表明,提出的新型锁存器电路不仅具有优秀的抗软错误能力,并且在功耗延迟积方面比现有的锁存器电路性能提升了26.74%~97.50%。
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出版历程
  • 收稿日期:  2017-03-03
  • 修回日期:  2017-07-07
  • 刊出日期:  2017-10-19

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