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椭圆曲线密码处理器的高效并行处理架构研究与设计

戴紫彬 易肃汶 李伟 南龙梅

戴紫彬, 易肃汶, 李伟, 南龙梅. 椭圆曲线密码处理器的高效并行处理架构研究与设计[J]. 电子与信息学报, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
引用本文: 戴紫彬, 易肃汶, 李伟, 南龙梅. 椭圆曲线密码处理器的高效并行处理架构研究与设计[J]. 电子与信息学报, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
Citation: DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380

椭圆曲线密码处理器的高效并行处理架构研究与设计

doi: 10.11999/JEIT161380
基金项目: 

国家自然科学基金(61404175)

Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 为了解决当前椭圆曲线密码处理器普遍存在灵活性低、资源占用大的问题,该文采用统计建模的方式,以面积-时间(AT)综合性能指标为指导,提出了一种面向椭圆曲线密码并行处理架构的量化评估方式,并确定3路异构并行处理架构可使处理器综合性能达到最优。其次,该文提出一个分离分级式存储结构和一个运算资源高度复用的模运算单元,可增强存储器的访问效率和运算资源的利用率。在90 nm CMOS工艺下综合,该文处理器的面积为1.62mm2,完成一次GF(2571)和GF(p521)上的点乘运算分别需要2.26 ms/612.4J和2.63 ms/665.4J。与同类设计相比,该文处理器不仅具有较高的灵活性、可伸缩性,而且其芯片面积和运算速度达到了很好的折中。
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出版历程
  • 收稿日期:  2016-12-21
  • 修回日期:  2017-03-06
  • 刊出日期:  2017-10-19

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