Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor
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摘要: 为了解决当前椭圆曲线密码处理器普遍存在灵活性低、资源占用大的问题,该文采用统计建模的方式,以面积-时间(AT)综合性能指标为指导,提出了一种面向椭圆曲线密码并行处理架构的量化评估方式,并确定3路异构并行处理架构可使处理器综合性能达到最优。其次,该文提出一个分离分级式存储结构和一个运算资源高度复用的模运算单元,可增强存储器的访问效率和运算资源的利用率。在90 nm CMOS工艺下综合,该文处理器的面积为1.62mm2,完成一次GF(2571)和GF(p521)上的点乘运算分别需要2.26 ms/612.4J和2.63 ms/665.4J。与同类设计相比,该文处理器不仅具有较高的灵活性、可伸缩性,而且其芯片面积和运算速度达到了很好的折中。Abstract: To overcome the common problem of low flexibility and much resource in Elliptic Curve Cryptographic (ECC) processor, a quantitative evaluation on Area-Time product (AT) for parallel processing architecture of ECC processor is proposed by statistics and modeling, and a conclusion that 3-way processing architecture is optimal can be drawn. Besides, a separated and hierarchical storage structure is exploited to strengthen the efficiency of data interaction. At the same time, a modular arithmetic unit is designed with a high level of resource reuse. Using 90 nm CMOS technology, the proposed processor occupied1.62mm2 can perform the scalar multiplication in2.26 ms/612.4J overGF(2571) and 2.63 ms/665.4 J overGF(p521), respectively. Compared to other works, this processor is advantageous not only in flexibility and scalability but also in making a good compromise between the hardware and the speed.
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